Dual-Stage CMP Planarization for High-K Gate Metal and Barrier Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The non-planarity of the surface in semiconductor components, particularly in MOS transistors, due to the use of high-K gate structures with barrier layers, affects the quality and performance by causing current leakage and increasing power consumption, necessitating a method to achieve a flat surface during manufacturing.
Innovation Solution
A planarization method involving sequential chemical mechanical polishing processes with specific etching reactants is applied to the metal and barrier layers, ensuring the etching rate of the reactants differs selectively to expose the dielectric layer, thereby achieving a flat surface by removing portions of the metal and barrier layers, with the first CMP process using a slurry with a lower oxidizer concentration and the second CMP process using a slurry with a higher oxidizer concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier layer and metal layer are formed on the dielectric layer to create a high-K gate structure, then current leakage is reduced and thermal stability is improved, but surface non-planarity occurs affecting MOS transistor quality
Solution Approach 1:
The planarization process is divided into two distinct stages: first CMP process targeting the metal layer with selective removal, and second CMP process targeting the barrier layer with different etching chemistry. This segmentation allows each process to be optimized for its specific material, achieving both complete metal removal and barrier layer planarity without compromising the underlying high-K dielectric structure.
Solution Approach 2:
The invention changes chemical parameters by using different CMP slurries with distinct etching rates and chemistries for different layers. The first slurry is optimized for metal layer removal with high etching rate, while the second slurry is optimized for barrier layer planarization with controlled etching rate, achieving selective planarization of each layer.
2Productivity
If the gate dielectric layer thickness is reduced to accommodate smaller channel sizes, then transistor performance is improved, but current leakage increases and power consumption rises
Solution Approach 1:
The invention changes the dielectric constant parameter by transitioning from traditional silicon oxide to high-K dielectric materials such as hafnium oxide or hafnium silicon oxynitride. This parameter change allows the gate dielectric layer to be physically thinner while maintaining or improving electrical performance, reducing leakage current and power consumption despite the reduced thickness.
3Stability of the object's composition
If a barrier layer is inserted between the metal gate and high-K dielectric layer to improve thermal stability, then thermal stability is enhanced, but surface non-planarity is introduced during manufacturing
Solution Approach 1:
The invention performs preliminary planarization actions through a two-stage CMP process. The first CMP process removes excess metal layer and prepares the surface, while the second CMP process planarizes the barrier layer surface before subsequent processing steps. This preliminary planarization ensures that the barrier layer, which is critical for thermal stability, is properly formed with good surface flatness.
Solution Approach 2:
The CMP slurry acts as an intermediary medium that enables selective removal and planarization of different layers. By using slurry chemistry as the intermediary, the process achieves differential etching rates between metal and barrier layer materials, allowing the barrier layer to be planarized without damaging the underlying high-K dielectric layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively eliminates surface dishing and achieves a flat surface with a height difference of less than 50 angstroms between the metal and dielectric layers, improving the quality and performance of semiconductor components by reducing current leakage and enhancing thermal stability.
Implementation Method 1
A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed to expose a portion of the barrier layer. An etching rate of the first reactant to the metal layer is greater than an etching rate of the first reactant to the barrier layer.
Implementation Method 2
A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and a portion of the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than an etching rate of the second reactant to the metal layer.
Implementation Method 3
A planarization method involving sequential chemical mechanical polishing processes with specific etching reactants is applied to the metal and barrier layers
Data Source
AI summary
A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.