Dual-Stage Comparator Switching for SAR ADC Speed and Noise
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Solution Overview
Problem
Successive approximation (SAR) analog-to-digital converters (ADCs) face limitations due to reduced transistor size and supply voltage, leading to slow decision-making in initial iterations and increased noise susceptibility as iterations progress, due to insufficient current handling and noise sensitivity.
Innovation Solution
A comparator with a bi-stable circuit and multiple amplification stages, switching between high-speed and low-noise modes based on common mode signal magnitude, using high-speed amplifiers for initial iterations to improve speed and low-noise amplifiers for subsequent iterations to reduce noise impact, while varying common mode signals to optimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single amplification stage is used in the comparator, then the device complexity is reduced, but the speed and noise performance cannot be optimized simultaneously for different iterations
Solution Approach 1:
The patent implements dynamic switching between high-speed and low-noise amplification stages based on the iteration phase. The comparator transitions from using the high-speed amplification stage during initial iterations to using the low-noise amplification stage in subsequent iterations, allowing the system to adapt its characteristics dynamically rather than being fixed. This resolves the contradiction by enabling speed optimization when needed and noise optimization when needed through time-varying configuration.
Solution Approach 2:
The patent divides the amplification function into two separate amplification stages: a high-speed amplification stage and a low-noise amplification stage. Instead of using a single amplification stage for all iterations, the system segments the amplification task and selects the appropriate stage based on the iteration phase. This segmentation allows independent optimization of speed and noise performance in different operational phases.
2Area of stationary object
If transistor size is reduced to increase integration density, then the area is reduced, but the current handling capability decreases leading to slow decision-making
Solution Approach 1:
The patent applies preliminary action by using the high-speed amplification stage during initial iterations to quickly establish the most significant bits of the conversion result. This preliminary high-speed operation compensates for the limited current handling capability of small transistors by providing a speed boost when it is most needed, before transitioning to the low-noise stage for finer precision work.
3Productivity
If the comparator operates at high speed during initial iterations, then the productivity is improved, but noise susceptibility increases during subsequent iterations
Solution Approach 1:
The patent implements periodic action by alternating between two operational modes: a high-speed mode during initial iterations and a low-noise mode during subsequent iterations. This periodic switching of operational characteristics allows the system to achieve high productivity when converting the most significant bits while minimizing noise susceptibility when converting less significant bits, thereby resolving the contradiction between speed and noise performance across different phases of the conversion process.
Data Source
AI summary
A comparator is described. The comparator may be used in several applications, including in digital-to-analog converters (ADC). The comparator may comprise a high-speed amplifier, a low-noise amplifier, a controller and a bi-stable circuit. The high-speed amplifier may be activated during a first period, for example when the comparator tends to exhibit a slow response. During this period, the comparator may sacrifice the noise performance. The low-noise amplifier may be activated during a second period, for example when the difference between the signals appearing as inputs to the comparator is small. The low-noise amplifier may have a gain that is large enough to limit decision errors. The bi-stable circuit, which may be implemented using a latch, may be configured to output a signal equal to one of the supply voltages, in response to receiving the input signal from one of the stages.