Dual-Stage Memory Decoding Circuit for Rewritable Non-Volatile Storage

Solution Overview

Problem

Existing decoding methods for rewritable non-volatile memory modules are slow when encountering error bits, as they require longer times to correct errors, hindering efficient data retrieval.

Innovation Solution

A decoding method utilizing two correcting circuits with different precisions, where a first correcting circuit performs a hard bit mode decoding procedure and, if unsuccessful, a second correcting circuit with higher precision performs a second decoding procedure, and the read voltage is adjusted based on syndrome information to optimize decoding speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single high-precision correcting circuit is used to ensure accurate error correction, then the reliability of data retrieval is improved, but the decoding time increases significantly

Engineering Contradiction:

Improveerror correction accuracyVSAvoiddecoding time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The correcting circuit is divided into two independent segments: a first correcting circuit with lower precision and faster operation, and a second correcting circuit with higher precision but slower operation. The system segments the error correction task into two stages, allowing the faster first circuit to handle simple cases and reserve the slower second circuit only for difficult cases that require higher precision.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically selects which correcting circuit to use based on the characteristics of the received signal. The controller determines whether to activate the first or second correcting circuit according to the error rate and signal quality, making the system adaptable rather than static. This dynamic selection optimizes the balance between speed and accuracy for each specific decoding scenario.

Inventive Principle:

Principle #15Dynamics

2Reliability

If a single high-precision correcting circuit is used to ensure accurate error correction, then the reliability of data retrieval is improved, but the productivity of data processing decreases

Engineering Contradiction:

Improveerror correction accuracyVSAvoiddata processing speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The correcting circuit is divided into two independent segments: a first correcting circuit with lower precision and faster operation, and a second correcting circuit with higher precision but slower operation. The system segments the error correction task into two stages, allowing the faster first circuit to handle simple cases and reserve the slower second circuit only for difficult cases that require higher precision.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically selects which correcting circuit to use based on the characteristics of the received signal. The controller determines whether to activate the first or second correcting circuit according to the error rate and signal quality, making the system adaptable rather than static. This dynamic selection optimizes the balance between speed and accuracy for each specific decoding scenario.

Inventive Principle:

Principle #15Dynamics

3Device complexity

If fixed read voltage is used for memory cell reading, then the device complexity is reduced, but the measurement precision of read data decreases

Engineering Contradiction:

Improveread voltage control complexityVSAvoidread data accuracy

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The read voltage is made dynamic rather than fixed. The system adjusts the read voltage based on feedback from the correcting circuits and the observed error patterns. This allows the read voltage to adapt to different memory cell states and error conditions, improving measurement precision without requiring complex manual intervention.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system implements a feedback mechanism where the correcting circuits analyze the read data and error patterns, then provide feedback to adjust subsequent read operations. This feedback loop enables automatic optimization of read voltage based on actual performance, improving precision while keeping the control system manageable through automated adjustment rather than complex manual control.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS9342404B2Decoding method, memory storage device, and memory controlling circuit unit

Publication Date: 2016.05.17 PHISON ELECTRONICS

AI summary

A decoding method, a memory storage device and a memory controlling circuit unit are provided. First, memory cells are read to obtain verification bits. A first hard bit mode decoding procedure is performed according to the verification bits and whether the first hard bit mode decoding procedure generates a first valid codeword is determined by a first correcting circuit. If the first valid codeword is generated, the first valid codeword is outputted. If the first valid codeword is not generated, a second hard bit mode decoding procedure is performed, and whether the second hard bit mode decoding procedure generates a second valid codeword is determined by a second correcting circuit. A precision of the first correcting circuit is less than a precision of the second correcting circuit. Accordingly, the speed of decoding is increased.