Dual-Stage Power Supply Layout for Mainboard Voltage Stability
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Solution Overview
Problem
The existing power supply structures on mainboards face challenges in meeting the dynamic response requirements of future processor chips due to increased voltage differences, higher power requirements, and spatial limitations, leading to inefficiencies and impedance issues that affect voltage stability and transmission efficiency.
Innovation Solution
The proposed solution involves a dual-stage power supply system where a preceding-stage DC-DC converter and multiple post-stage DC-DC converters are strategically placed on the same side of the chip, with overlapping profiles to reduce impedance and increase efficiency, allowing for parallel input and output power distribution to minimize voltage fluctuations and impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the bus voltage is increased to 48V or 400V to reduce transmission loss, then power transmission efficiency is improved, but the voltage difference between input and output of the power supply increases, making power supply to the processor chip more difficult
Solution Approach 1:
The power supply system is divided into two stages: a first power supply module that converts high-voltage input (48V or 400V) to an intermediate voltage, and a second power supply module that converts the intermediate voltage to the final low voltage for the processor chip. This segmentation allows the system to benefit from high-voltage transmission efficiency while managing the voltage conversion complexity in distributed stages.
Solution Approach 2:
The patent transitions from a planar layout to a three-dimensional stacked configuration where the first and second power supply modules are positioned at different vertical levels on the mainboard. This spatial dimensionality change reduces the transmission distance and impedance between modules, addressing the complexity issue while maintaining high-voltage input benefits.
2Adaptability or versatility
If the voltage is continuously reduced to meet processor chip requirements (e.g., 0.8V for 14nm, 0.6V for 10nm), then compatibility with advanced processor chips is improved, but the power supply current increases, requiring higher current capability from the power supply system
Solution Approach 1:
The two-stage power supply architecture segments the voltage conversion process, with the first module handling the high-voltage-to-intermediate conversion and the second module handling the intermediate-to-low-voltage conversion. This segmentation allows each stage to be optimized for its specific voltage range, managing the high current requirements at the low-voltage stage while maintaining adaptability to different processor chip voltage requirements.
Solution Approach 2:
The patent employs parameter changes by adjusting the intermediate voltage level between the two stages and optimizing the electrical characteristics (such as trace width, layer configuration, and impedance control) of the power transmission path to handle the increased current while maintaining voltage stability for different processor chip generations.
3Loss of energy
If the first and second power supply modules are placed closer to high-speed signal lines to reduce impedance, then transmission efficiency is improved, but electromagnetic interference with the high-speed signal lines increases
Solution Approach 1:
The patent applies local quality by creating different electromagnetic environment zones: the first power supply module operates in a region with higher electromagnetic tolerance, while the second power supply module, which handles lower voltages and higher currents, is positioned with enhanced electromagnetic shielding and grounding structures. This localized optimization allows close placement to reduce impedance while managing EMI through targeted shielding measures.
Solution Approach 2:
The patent introduces electromagnetic shielding structures, ground planes, and filtering circuits as intermediary elements between the power supply modules and the high-speed signal lines. These intermediaries act as buffers that allow the power modules to be positioned close to signal lines for low impedance while preventing harmful electromagnetic interference from affecting the sensitive signal transmission.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces voltage fluctuations by half, decreases transmission impedance, and allows for a more compact design that can be closer to high-speed signal lines, enhancing dynamic response performance and power supply efficiency.
Implementation Method 1
The DC-DC converter is configured to receive an input voltage and to transform the input voltage into an output voltage
Data Source
AI summary
The disclosure provides a system of providing power to a chip on a mainboard. The system comprises at least one preceding-stage power supply module located on a surface of a mainboard, being DC-DC converters, and configured to receive a first DC voltage and to provide a second DC voltage; and at least one post-stage power supply module located on the same surface of the preceding-stage power supply module of the mainboard. Wherein the post-stage power supply module is electrically connected to the preceding-stage power supply module to receive the second DC voltage, the preceding-stage power supply module and the post-stage power supply module are disposed at same side of the chip, the post-stage power supply module provides a third DC voltage to the chip. A profile projection of the preceding-stage power supply module and the corresponding post-stage power supply module are overlapped with each other over 50%.