Dual-Stage Data Scrambling for Embedded Memory Security
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Solution Overview
Problem
Existing data scrambling methods in embedded devices are vulnerable to brute force key attacks and chosen plaintext attacks, particularly due to limitations in key length and complexity, which can be exploited by attackers to uncover the scramble algorithm.
Innovation Solution
A data processing apparatus with a dual-stage scrambling mechanism using two XOR circuits and substitution function processing units, where the key length is effectively doubled by using separate scramble key data for each stage, enhancing resistance to brute force and chosen plaintext attacks while maintaining high-speed processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-stage scrambling method is used, then the device complexity is low, but the resistance to brute force key attacks and chosen plaintext attacks is insufficient
Solution Approach 1:
The scrambling operation is divided into two distinct stages: a first scrambling operation using first scramble key data, and a second scrambling operation using second scramble key data. This segmentation increases the effective key length and resistance to attacks while maintaining manageable device complexity through modular design of the scramble unit.
2Reliability
If the key length is increased to resist brute force attacks, then the security improves, but the processing speed decreases
Solution Approach 1:
The scrambling is segmented into two stages with separate key data, effectively doubling the key length without requiring a single complex cryptographic operation. Each stage can be processed independently, maintaining high processing speed while achieving enhanced security resistance.
3Reliability
If a complex scrambling algorithm is used, then the resistance to chosen plaintext attacks improves, but the processing complexity and time increase
Solution Approach 1:
The scrambling algorithm is divided into two sequential operations with different key data. This segmentation provides resistance to chosen plaintext attacks without requiring a single overly complex algorithm, as each stage can be independently optimized and processed.
Data Source
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AI summary
A data processing apparatus includes an address bus, a scramble unit, and a data bus. The address bus outputs address data to be given to a memory apparatus. The scramble unit scrambles write-in data into a storage position in the memory apparatus identified by the address data to obtain confidential data. The data bus outputs the confidential data. The scramble unit includes a first scramble unit, a first conversion unit and a second scramble unit. The first scramble unit XORs first mask data corresponding to the address data and the write-in data for each bit and makes it first scrambled data. The first conversion unit performs one-to-one substitution conversion of the first scrambled data. The second scramble unit XORs second mask data corresponding to the address data and data after the conversion of the first scrambled data by the first conversion unit and outputs obtained second scrambled data as the confidential data.