Dual-Stage Sensing Circuit for MRAM Offset Cancellation
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Solution Overview
Problem
Conventional sensing circuits in magnetoresistive random access memory (MRAM) face challenges with degraded sensing margins due to technology scaling, process variations, and limited sensing current, leading to poor performance and manufacturing issues, particularly in irregular array structures that require special reference cells and result in regularity problems, additional costs, and design complexity.
Innovation Solution
A dual-stage sensing circuit with a regular array structure that uses selectively coupled resistor cells (RL/RH cells) identical to the data cells, allowing for offset voltage cancellation without requiring irregular structures, thereby improving sensing accuracy and reducing design complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional sensing circuits are used in MRAM, then the circuit can perform basic read operations, but the sensing margin is degraded due to technology scaling, process variation, and limited sensing current
Solution Approach 1:
The sensing operation is divided into two distinct stages: a first sensing stage that performs initial differential sensing, and a second sensing stage that performs offset cancellation. This segmentation allows each stage to be optimized for its specific function, improving overall sensing margin while maintaining performance.
Solution Approach 2:
The first sensing stage performs preliminary differential sensing to establish initial voltage differences before the second stage performs offset cancellation. This preliminary action prepares the circuit state for more accurate final sensing, effectively combating process variation effects.
2Measurement precision
If offset tolerant sensing circuits are used to overcome sensing margin degradation, then sensing accuracy is improved, but the circuit complexity increases due to multi-stage sensing operation
Solution Approach 1:
The circuit merges differential sensing and offset cancellation functions into a unified dual-stage sensing architecture that shares common circuit elements and control logic. This merging approach achieves offset tolerance and high sensing accuracy while minimizing the increase in circuit complexity compared to fully separate circuits.
Solution Approach 2:
The sensing circuit is designed with multi-functional elements that can operate in different modes: the same circuit components perform both differential sensing in the first stage and offset cancellation in the second stage. This universality reduces the need for additional dedicated components, thereby limiting complexity growth.
3Measurement precision
If irregular array structure with special reference cells is used, then offset voltage cancellation is achieved, but manufacturing cost and design complexity increase
Solution Approach 1:
The invention uses regular array structures with homogeneous cell designs throughout, eliminating the need for special irregular reference cells. All memory cells follow the same layout and fabrication rules, which simplifies manufacturing processes, reduces design complexity, and lowers production costs while still achieving offset voltage cancellation through the dual-stage sensing method.
Solution Approach 2:
Instead of using special reference cells with different structures, the invention creates virtual reference signals by copying and reusing standard cell structures in the regular array. The dual-stage sensing circuit processes signals from regularly-structured cells to achieve offset cancellation, avoiding the need for physically different reference cell implementations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively cancels out offset voltages, maintains sensing accuracy, and simplifies design without additional costs or regularity issues, enhancing the performance of MRAM sensing circuits.
Implementation Method 1
A magnetic tunnel junction (MTJ), which is conventionally used as a storage element or bit cell for MRAM technology, can be formed from two magnetic layers, each of which can hold a magnetic moment, separated by an insulating (tunnel barrier) layer. A change in the polarity of the free layer will change the resistance of the MTJ bit cell.
Implementation Method 2
In order to read the bit cell, a sensing current is passed through the bit cell and a voltage Vdata developed across the resistance Rdata is then compared to a reference voltage Vref.
Data Source
AI summary
A sensing system may include a sense amplifier, a sensing circuit configured to sense a current difference, a data cell selectively coupled to the sensing circuit, a first reference cell selectively coupled to the sensing circuit, and a second reference cell selectively coupled to the sensing circuit. The resistance of the first reference cell and the second reference cell are different.