3D Memory Stair-Step Formation for Dense Wordline Coupling
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Solution Overview
Problem
Current memory circuitry technologies face challenges in achieving high circuit density and efficient electrical coupling of memory cells, particularly in the formation of stair-step structures for vertically-stacked memory cells, which affects the performance and accessibility of memory arrays.
Innovation Solution
The method involves forming a stack with vertically-alternating conductive and insulative tiers, using multiple mask-patterning steps and imageable resist layers to create stair-step structures with optimized pitch and depth configurations, allowing for direct electrical coupling of channel material strings and enabling increased circuit density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional stair-step structures are used for vertically-stacked memory cells, then electrical coupling of memory cells is achieved, but circuit density is limited due to larger pitch requirements
Solution Approach 1:
The patent transitions from conventional two-dimensional planar stair-step structures to a three-dimensional configuration where the stair-step structure extends vertically through multiple tiers. This dimensional change allows the same electrical coupling function to be achieved with reduced lateral pitch, thereby increasing circuit density. The stair-step structure now occupies vertical space to reduce horizontal footprint.
Solution Approach 2:
The patent implements a nested configuration where the stair-step structure is embedded within and integrated with the vertically-stacked memory cell array. The conductive tiers of the stair-step structure are nested between the memory cell stacks, allowing shared use of vertical space and reducing the overall lateral dimensions required for the memory array.
2Manufacturing precision
If multiple mask-patterning steps are used to form optimized stair-step structures, then pitch and depth are optimized for higher density, but manufacturing complexity increases
Solution Approach 1:
The patent divides the formation of the stair-step structure into multiple discrete mask-patterning steps, where each step creates a specific tier or portion of the final structure. This segmentation allows precise control over the pitch and depth of each individual tier, enabling optimized configurations for high-density memory while maintaining manufacturability through systematic, step-by-step fabrication.
Solution Approach 2:
The patent performs preliminary patterning actions to define the stair-step structure before final memory cell formation. By pre-establishing the conductive tiers and their geometric configurations in advance, subsequent fabrication steps can proceed with greater precision and fewer adjustments, effectively managing the complexity of multiple patterning steps through strategic sequencing.
3Productivity
If vertically-stacked memory cells are implemented, then three-dimensional integration is achieved, but electrical accessibility to wordlines becomes more difficult
Solution Approach 1:
The patent introduces the stair-step structure as an intermediary element that provides electrical access to the wordlines of vertically-stacked memory cells. The conductive tiers of the stair-step structure act as intermediate connection points, allowing external electrical signals to reach the deeply embedded wordlines without requiring complex through-silicon vias or other intricate access mechanisms. This intermediary structure simplifies the electrical interface to three-dimensional memory arrays.
Data Source
AI summary
A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A first layer of imageable resist is exposed to actinic radiation and developed to form a first opening there-through in the stair-step region. The developed first layer is used in a plurality of alternating etching and lateral-trimming steps that widens the first opening and forms two opposing flights of stairs in the stack in the stair-step region. A second layer of imageable resist is formed directly above the two opposing flights of stairs. The second layer is exposed to actinic radiation and developed to form a second opening there-through. The second opening exposes all of the stairs of one of the two opposing flights. The second layer is directly above all of the stairs in the other of the two opposing flights. The developed second layer is used in a plurality of alternating etching and lateral-trimming steps that widens the second opening, lengthens at least one of the two opposing flights of stairs, and extends the two opposing flights of stairs deeper into the stack. Other embodiments, including structure, are disclosed.