Dual-Station Semiconductor Lithography for Reduced Wafer Occupancy
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Solution Overview
Problem
Existing semiconductor lithography systems face inefficiencies in processing time and resource utilization due to the sequential patterning of all regions of a semiconductor wafer at a single station, which can lead to increased production time and reduced yield.
Innovation Solution
A dual-station approach is implemented, where a photolithographic pattern is written at one station and a mask-less direct-beam write pattern is written at a separate station, allowing for concurrent processing of different regions of the wafer, thereby reducing the time a wafer occupies a single station and optimizing resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all regions of a semiconductor wafer are patterned sequentially at a single station, then the patterning process can be completed with a single system configuration, but the production time increases and resource utilization decreases
Solution Approach 1:
The patent divides the wafer into different regions (first region and second region) and patterns them at different stations (first photolithography station and second direct-beam write station). This segmentation allows parallel processing of different regions, reducing overall production time while maintaining system functionality through distributed processing capabilities.
2Productivity
If a single photolithography station processes the entire wafer, then the system configuration is simpler, but resource utilization is reduced and production efficiency decreases
Solution Approach 1:
The patent combines photolithography and direct-beam write capabilities into a single integrated system with multiple stations that can process different regions simultaneously. This merging of different patterning technologies in one system improves resource utilization by allowing both stations to operate concurrently on the same wafer, reducing idle time and increasing overall productivity.
3Loss of time
If sequential patterning is used at a single station, then the process flow is simpler, but wafer occupancy time increases
Solution Approach 1:
The patent implements continuous processing by having the first photolithography station and second direct-beam write station operate simultaneously on different regions of the wafer. This eliminates idle time between patterning operations and maintains continuous useful action throughout the process, significantly reducing total wafer occupancy time while managing complexity through automated station coordination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances processing efficiency by reducing wafer occupancy time at a single station and improves yield by allowing for more predictable and uniform semiconductor fabrication processes, particularly through the use of dummy patterns in non-dummy regions to maintain consistent pattern density and dimensions.
Implementation Method 1
patterning a first region of the first semiconductor wafer by directing light from a light source through transparent regions of an optical mask
Implementation Method 2
patterning a second region of the first semiconductor wafer by directing energy from a direct-beam writer to the second region
Data Source
AI summary
A lithography method to pattern a first semiconductor wafer is disclosed. An optical mask is positioned over the first semiconductor wafer. A first region of the first semiconductor wafer is patterned by directing light from a light source through transparent regions of the optical mask. A second region of the first semiconductor wafer is patterned by directing energy from an energy source to the second region, wherein the patterning of the second region comprises direct-beam writing.