Dual-Strain Semiconductor Substrate for Stacked CMOS Mobility
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in enhancing transistor density and mobility by effectively stacking complementary metal-oxide-semiconductor (CMOS) structures with strain engineering, as existing methods struggle to optimize the strain levels in silicon germanium (SiGe) layers for improved performance of N-channel and P-channel field effect transistors.
Innovation Solution
The implementation of a semiconductor structure with compressively strained SiGe layers and tensely strained silicon layers, where SiGe layers are epitaxially grown and selectively undercut to create a stacked fin field-effect transistor (FinFET) or nanosheet CMOS structure, allowing for enhanced electron and hole mobility by strategically layering compressively strained SiGe and tensely strained silicon layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SiGe layers are grown to enhance transistor mobility through strain engineering, then carrier mobility improves, but controlling uniform strain distribution becomes difficult
Solution Approach 1:
The patent segments the SiGe layer into multiple discrete layers (first SiGe layer, second SiGe layer, third SiGe layer) with different germanium concentrations and positions. This segmentation allows each layer to contribute differently to the overall strain distribution, enabling precise control over strain uniformity across the transistor channel while maintaining high carrier mobility.
Solution Approach 2:
The patent applies local quality by varying the germanium concentration and positioning of SiGe layers at different locations within the transistor structure. The first SiGe layer has a first germanium concentration, the second SiGe layer has a second germanium concentration, and the third SiGe layer has a third germanium concentration, creating locally optimized strain conditions for both n-type and p-type transistors.
2Productivity
If multiple SiGe layers are stacked to increase transistor density, then device integration increases, but process complexity increases
Solution Approach 1:
The patent implements nested doll by stacking multiple SiGe layers (first, second, and third SiGe layers) with different properties within a single transistor structure. Each SiGe layer is nested within the overall stack, with intermediate dielectric layers providing isolation. This nested structure enables high transistor density by vertically integrating multiple functional layers without requiring separate processing for each transistor type.
Solution Approach 2:
The patent achieves universality by creating a multi-functional stacked structure where the same layer stack serves both n-type and p-type transistors. The combination of compressively strained and tensely strained SiGe layers provides the strain necessary for both transistor types, eliminating the need for separate processing streams and simplifying manufacturing while increasing density.
3Reliability
If compressively strained SiGe and tensely strained Si are combined in stacked FinFETs, then both NFET and PFET performance improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating distinct strain conditions in different regions of the stacked structure. The first SiGe layer provides compressive strain for p-type transistors, while the second and third SiGe layers provide tensile strain for n-type transistors. Each region is locally optimized for its specific transistor type, achieving high performance for both NFET and PFET while managing strain control through localized material properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases transistor density and improves the performance of both N-channel and P-channel field effect transistors by optimizing strain levels, leading to enhanced mobility and overall performance of CMOS structures.
Implementation Method 1
A first silicon germanium (SiGe) layer is epitaxially grown on top of a substrate. A second silicon germanium (SiGe) layer is epitaxially grown on top of the first SiGe layer. A third silicon germanium (SiGe) layer is epitaxially grown on top of the second SiGe layer.
Data Source
AI summary
A dielectric layer is on top of a first semiconductor stack. The first semiconductor stack is compressively strained. A second semiconductor stack is on top of the dielectric layer. The second semiconductor stack is tensely strained.