Dual Strained Cladding Layers for CMOS FinFET Carrier Mobility
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing carrier mobility for both p-type and n-type fins in CMOS technology due to differences in material characteristics, leading to inefficient strained cladding layer application that affects performance and energy consumption.
Innovation Solution
The implementation of a dual strained cladding layer approach, where p-type and n-type semiconductor bodies receive distinct cladding layers based on their carrier type, with Ge or SiGe for p-type and Si for n-type, respectively, grown using selective epitaxial processes to achieve strain and improve mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single strained cladding layer material is used for both p-type and n-type fins, then the manufacturing process is simplified, but carrier mobility enhancement is insufficient for one or both transistor types
Solution Approach 1:
The patent applies different cladding layer materials to different fin types: Ge or SiGe for p-type fins and Si for n-type fins. This local differentiation optimizes carrier mobility for each transistor type specifically, with Ge/SiGe providing compressive strain for holes and Si providing tensile strain for electrons, rather than using a uniform material across all fins
Solution Approach 2:
The manufacturing process is segmented into separate epitaxial growth steps for p-type and n-type fins. The method involves selectively forming cladding layers on alternating fins through multiple deposition cycles, allowing independent optimization of each fin type's strain characteristics
2Reliability
If Ge or SiGe cladding layer is applied to p-type fins, then hole mobility is enhanced through compressive stress, but electron mobility in n-type fins remains unoptimized
Solution Approach 1:
The patent tailors the cladding layer material composition to the specific carrier type in each fin: Ge or SiGe with higher Ge content for p-type fins to maximize compressive strain for hole transport, and pure Si for n-type fins to provide appropriate tensile strain for electron transport
Solution Approach 2:
The patent uses composite material structures where SiGe fins are combined with different cladding materials (Ge or Si) depending on the desired carrier type. This composite approach allows simultaneous optimization for both p-type and n-type transistors within the same CMOS device
3Reliability
If Si cladding layer is applied to n-type fins, then electron mobility is enhanced through tensile stress, but hole mobility in p-type fins remains unoptimized
Solution Approach 1:
The patent applies pure Si cladding layers specifically to n-type fins where tensile strain is optimal for electron mobility enhancement, while reserving Ge or SiGe cladding for p-type fins where compressive strain benefits hole transport
Solution Approach 2:
The patent employs dynamic control of the epitaxial growth process, alternating between depositing Si and Ge/SiGe layers in sequence to create different strain environments for adjacent fins, enabling the structure to adapt to different carrier types spatially
4Reliability
If selective epitaxial growth is used to form different cladding layers on alternating fins, then carrier mobility is optimized for both transistor types, but manufacturing complexity increases
Solution Approach 1:
The patent divides the fin structure into alternating p-type and n-type fins that are processed in separate epitaxial steps, allowing independent material selection and strain optimization for each fin type while maintaining a unified device architecture
Solution Approach 2:
The patent performs preliminary selective epitaxial growth of cladding layers before final device assembly, establishing the strain profile early in the manufacturing process to guide subsequent processing steps and ensure optimal carrier mobility from the outset
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances hole and electron mobility, resulting in improved performance and reduced energy consumption, with PMOS devices experiencing compressive stress and NMOS devices experiencing tensile stress, leading to substantial gains in carrier mobility compared to non-cladded structures.
Implementation Method 1
grown using selective epitaxial processes to achieve strain and improve mobility
Implementation Method 2
PMOS devices experiencing compressive stress and NMOS devices experiencing tensile stress, leading to substantial gains in carrier mobility
Data Source
AI summary
Techniques and methods related to dual strained cladding layers for semiconductor devices, and systems incorporating such semiconductor devices.