Dual Strained Nanosheet CMOS Fabrication
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Solution Overview
Problem
Existing semiconductor devices face challenges in enhancing both electron and hole mobility for CMOS structures using gate-all-around (GAA) nanosheet structures, particularly in suspending nanosheet structures, which leads to degraded electron mobility due to low-mobility sidewalls and scattering mechanisms.
Innovation Solution
The method involves growing a lattice of alternating tensile strained silicon and relaxed silicon-germanium sheets on a substrate, isolating portions to form PFET and NFET structures, selectively removing silicon-germanium and silicon layers, and increasing germanium content in the relaxed silicon-germanium layers using a low temperature condensation process, followed by filling voids with high k dielectric/metal gate material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-all-around (GAA) nanosheet structures are used to improve electrostatics and immunity to short channel effects, then device performance is improved, but electron mobility is degraded due to low-mobility sidewalls and scattering mechanisms
Solution Approach 1:
The patent applies different materials to different regions of the nanosheet structure. Specifically, silicon-germanium (SiGe) nanosheets are used for PFET devices where hole mobility is needed, while silicon (Si) nanosheets are used for NFET devices where electron mobility is critical. This local differentiation allows each region to have optimized properties for its specific function, resolving the contradiction between improved electrostatics and maintained electron mobility.
Solution Approach 2:
The patent employs composite material structures combining silicon and silicon-germanium in alternating nanosheet layers. The Si/SiGe composite structure allows the device to leverage the advantages of both materials: Si provides high electron mobility for NFET operation, while SiGe provides good hole mobility for PFET operation. Both materials contribute to the overall electrostatic control and short channel effect immunity of the GAA structure.
2Speed
If alternating sheets of tensile strained silicon and relaxed silicon-germanium are grown to enable strain engineering, then mobility can be improved, but the thickness difference between layers increases, complicating fabrication
Solution Approach 1:
The patent carefully controls and adjusts the thickness parameters of both silicon and silicon-germanium nanosheets during the epitaxial growth process. By optimizing growth conditions and duration, the patent achieves thickness uniformity across alternating layers despite the inherent lattice mismatch between Si and SiGe. This parameter control enables strain engineering benefits while maintaining manufacturability.
3Speed
If selective removal of silicon-germanium layers is performed to form NFET structures, then n-type device performance is improved, but additional fabrication steps are required
Solution Approach 1:
The patent segments the alternating Si/SiGe nanosheet lattice into distinct regions for NFET and PFET formation. By applying masks and performing selective removal operations on specific segments of the lattice, the patent creates NFET structures where SiGe layers are removed to expose Si nanosheets, while PFET regions retain the full Si/SiGe structure. This segmentation approach enables differentiated device formation from a unified starting structure.
Solution Approach 2:
The patent performs preliminary actions by forming the complete alternating Si/SiGe nanosheet lattice structure before any selective removal operations. The lattice is fully grown with both material types in place, and then subsequent selective removal steps are applied to create different device types. This preliminary formation of the complete structure simplifies the overall process by establishing a standardized starting point for all device variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves mobility by achieving strain engineering, enhancing electrostatics, and reducing thickness differences between silicon and silicon-germanium layers, resulting in improved performance for 5 nanometer technology and beyond.
Implementation Method 1
performing a low temperature condensation process to increase a germanium content in the relaxed silicon-germanium layers in the first portion of the lattice
Implementation Method 2
epitaxially forming alternating sheets of tensile strained silicon and relaxed silicon-germanium on the strained relaxed buffer layer to form a lattice
Data Source
AI summary
A method includes: growing a lattice of alternating sheets of tensile strained silicon and relaxed silicon-germanium on a substrate; isolating a first portion of the lattice from a second portion of the lattice; forming source regions and drain regions on each of the first portion of the lattice and the second portion of the lattice; forming a first gate opening in the first portion of the lattice and a second gate opening in the second portion of the lattice; selectively removing the sheets of relaxed silicon-germanium from under the second gate opening in the second portion of the lattice; selectively removing portions of the sheets of tensile strained silicon from under the first gate opening in the first portion of the lattice; and increasing a germanium content in the relaxed silicon-germanium layers under the first gate opening in the first portion of the lattice.