Dual Stress Layer Semiconductor Structure for Channel Optimization
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Solution Overview
Problem
Current semiconductor devices face challenges in improving performance due to insufficient stress on the channel, leading to low driving current and poor short-channel effects, despite advancements in integrated circuit manufacturing.
Innovation Solution
A semiconductor structure is developed with a first stress layer on the sidewall and a second stress layer at the bottom of the source-drain opening, where the second stress layer fully fills the opening and has higher stress than the first layer, optimizing the volume and stress contribution to the channel while reducing interface defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a single stress layer is formed in the source-drain opening, then the manufacturing process is simple, but the stress contribution to the channel is insufficient and driving current is low
Solution Approach 1:
The stress layer is divided into two distinct segments: a first stress layer formed on the sidewall of the source-drain opening and a second stress layer formed at the bottom of the source-drain opening. This segmentation allows each layer to contribute stress independently to the channel, increasing the total stress and driving current while maintaining a manageable structural complexity.
Solution Approach 2:
Different regions of the source-drain opening are assigned different stress layer configurations. The sidewall region receives the first stress layer while the bottom region receives the second stress layer. This local differentiation optimizes stress distribution to the channel, enhancing carrier mobility and driving current without requiring uniform complexity throughout the entire structure.
2Reliability
If the source-drain opening is fully filled with stress layer material, then the stress contribution is maximized, but interface defects increase due to direct contact with the substrate
Solution Approach 1:
The first stress layer formed on the sidewall acts as an intermediary between the substrate and the second stress layer that fills the bottom of the source-drain opening. This intermediate layer reduces direct interface defects between the second stress layer and the substrate, improving the short-channel effect and overall device reliability while still allowing the second stress layer to provide maximum stress contribution.
3Power
If stress layer material is deposited to fully fill the source-drain opening, then the volume and stress contribution are increased, but the driving current remains low due to insufficient stress
Solution Approach 1:
Instead of only increasing the volume of stress layer material in a single configuration, the invention utilizes three-dimensional spatial arrangement by forming stress layers on both the sidewall and bottom of the source-drain opening. This dimensional approach ensures that stress is applied from multiple directions to the channel, maximizing the stress effect and thereby increasing driving current more effectively than volume increase alone.
Data Source
AI summary
A semiconductor structure and a method for forming the semiconductor structure are provided. The semiconductor structure includes a substrate and a dummy gate structure on the substrate. The substrate contains source-drain openings on both sides of the dummy gate structure. The semiconductor structure also includes a first stress layer formed on a sidewall of a source-drain opening of the source-drain openings. Further, the semiconductor structure includes a second stress layer formed at a bottom of the source-drain opening and on the first stress layer. The second stress layer fully fills the source-drain opening, and stress of the first stress layer is less than stress of the second stress layer.