Dual Stress-Relieving Structure for Semiconductor Device
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Solution Overview
Problem
The scaling down of semiconductor devices poses challenges in achieving improved quality, yield, performance, and reliability due to stress issues during wiring, solder bump formation, and packaging processes, which can lead to cracking and delamination of interconnection films.
Innovation Solution
The semiconductor device incorporates a dual stress-relieving structure comprising a conductive frame and insulating pillars, along with a conductive structure featuring a supporting portion and spacers, to mitigate stress and prevent delamination, thereby enhancing the device's reliability and quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor device dimensions are scaled down to improve computing ability, then device density and computing performance are improved, but stress issues during manufacturing processes worsen leading to cracking and delamination
Solution Approach 1:
The patent divides the stress-relieving structure into multiple segments: a first stress-relieving structure with conductive frame and insulating pillars, and a second stress-relieving structure with conductive pillars and insulating frame. This segmentation allows each structure to independently manage stress in different regions, preventing cracking and delamination while maintaining device reliability during scaling down
Solution Approach 2:
The patent applies different material properties to different parts of the stress-relieving structures. The first insulating pillars have a higher dielectric coefficient than the second insulating frame, creating local variations in stress distribution. This local quality differentiation enables targeted stress management in specific device regions, preventing manufacturing defects while maintaining overall device performance
2Reliability
If dual stress-relieving structures with different dielectric coefficients are implemented, then stress distribution is improved preventing cracking and delamination, but device complexity increases
Solution Approach 1:
The first and second stress-relieving structures serve multiple functions: they provide mechanical stress relief, act as insulating barriers, and serve as structural support frameworks. By combining these functions into unified structures, the patent reduces the need for separate components, thereby managing complexity while achieving improved stress distribution and preventing manufacturing defects
Data Source
AI summary
The present application provides a method for fabricating a semiconductor device including providing a semiconductor substrate, forming a first stress-relieving structure including a first conductive frame above the semiconductor substrate and a plurality of first insulating pillars within the first conductive frame, forming a second stress-relieving structure comprising a plurality of second conductive pillars above the first stress-relieving structure and a second insulating frame, the plurality of second conductive pillars are disposed within the second conductive frame, wherein the plurality of second conductive pillars is disposed correspondingly above the plurality of first insulating pillars, and the second insulating frame is disposed correspondingly above the first conductive frame; and forming a conductive structure including a supporting portion above the second stress-relieving structure, a conductive portion adjacent to the supporting portion, and a plurality of spacers attached to two sides of the conductive portion.