Dual Stress-Inducing Layers for Semiconductor Wafer Bonding
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Solution Overview
Problem
Integrated semiconductor devices are prone to damage during thinning processes due to undesired stress-induced bowing and void formation between wafers, leading to reduced yield and potential cracking or delamination.
Innovation Solution
A method involving the use of two stress-inducing layers with different stresses, where a compressive silicon nitride layer and a tensile silicon oxide layer are applied to the substrate to bend it into a bow-shape, allowing for a smoother bonding front and preventing voids and gases from forming during the thinning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If a single stress-inducing layer is used to bend the substrate, then the substrate can be pre-shaped, but undesired stress-induced bowing with unsmooth bonding front occurs leading to void formation
Solution Approach 1:
The single stress-inducing layer is segmented into two distinct layers: a first stress-inducing layer (compressive) and a second stress-inducing layer (tensile). This segmentation allows independent control of stress characteristics, enabling the substrate to be bent into a desired bow shape while maintaining a smooth bonding front during wafer bonding, thereby preventing void formation.
Solution Approach 2:
Different regions of the substrate are subjected to different stress characteristics through the two-layer structure. The compressive first layer and tensile second layer create localized stress distributions that can be optimized for specific bonding requirements, allowing precise control over the bonding front propagation and substrate shape.
2Reliability
If bonding pressure is applied to affix carrier wafer to device wafer, then the wafers are bonded together, but void and gases are trapped between the bonded wafers due to unsmooth bonding front
Solution Approach 1:
The substrate is pre-bent into a desired bow shape using the two stress-inducing layers before the bonding process. This preliminary action ensures that when bonding pressure is applied, the bonding front propagates smoothly from center to edge, preventing void and gas trapping that would otherwise occur with uncontrolled substrate deformation during bonding.
3Volume of moving object
If the device wafer is thinned to reduce package height, then smaller integrated semiconductor devices are achieved, but the wafer becomes vulnerable to cracking and breakage
Solution Approach 1:
The two stress-inducing layers are applied to the substrate beforehand to create a controlled bow shape that compensates for the mechanical weakness of thinned wafers. This pre-engineered stress structure acts as a cushioning mechanism, distributing stresses during handling and processing to prevent cracking and breakage in the thinned device wafer.
4Manufacturing precision
If the substrate is bent into bow-shape using stress-inducing layers, then smoother bonding front is achieved, but additional process steps are required
Solution Approach 1:
The formation of the two stress-inducing layers is merged with the existing substrate preparation process flow. The compressive first layer and tensile second layer are deposited using standard semiconductor fabrication techniques, integrating the substrate shaping function into the existing manufacturing process without requiring entirely new equipment or methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the yield of integrated semiconductor devices by preventing damage during thinning and ensuring a smoother contact wave during bonding, reducing the likelihood of cracking and delamination.
Implementation Method 1
a first stress-inducing layer, a second stress-inducing layer... The first stress-inducing layer is a compressive stress layer, and the second stress-inducing layer is a tensile stress layer
Data Source
AI summary
An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate.