Dual-Structure Clock Tree Synthesis for OCV Skew Control
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Solution Overview
Problem
Conventional clock tree synthesis approaches fail to effectively address on-chip variation (OCV) impacts on clock skew, leading to variations in clock signal distribution across a chip, which affects timing closure and circuit performance.
Innovation Solution
A dual-structure clock tree synthesis method is introduced, where upper-level clock trees are optimized to reduce OCV and cross-corner variations, and lower-level clock trees are optimized for reduced latency, power consumption, and area, with all horizontal wires routed on the same metal layer and all vertical wires on another, using identical buffer sizes to minimize skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock tree synthesis is used, then the clock distribution network can be created, but it fails to effectively address on-chip variation impacts on clock skew
Solution Approach 1:
The patent divides the clock tree into upper-level and lower-level structures. The upper-level clock trees are optimized to reduce OCV impact on clock skew, while the lower-level clock trees are optimized for latency, power consumption, and area. This segmentation allows different parts of the clock tree to serve different functions and be optimized accordingly.
Solution Approach 2:
The patent applies different optimization strategies to different levels of the clock tree. The upper-level trees use strategies tailored for reducing OCV impact (such as specific buffer sizing and routing), while the lower-level trees use strategies for minimizing latency and power. This local quality approach allows each part to be optimized for its specific requirements.
2Reliability
If upper-level clock trees use wider wires and specific metal layer routing, then OCV impact on clock skew is reduced, but device complexity increases
Solution Approach 1:
The patent segments the clock tree into upper-level and lower-level structures with different optimization characteristics. The upper-level trees use wider wires and specific metal layer routing to reduce OCV impact, while the lower-level trees use different strategies for latency and power optimization. This segmentation allows the system to manage complexity by dividing the overall structure into manageable parts with specialized optimization.
Solution Approach 2:
The patent changes physical parameters such as wire width and metal layer assignment in the upper-level clock trees to reduce OCV impact. By adjusting these parameters specifically in the upper levels rather than throughout the entire tree, the patent achieves better clock skew control while managing the overall device complexity.
3Productivity
If lower-level clock trees are optimized for reduced latency and power consumption, then performance improves, but OCV impact on clock skew increases
Solution Approach 1:
The patent segments the clock tree optimization responsibilities between upper-level and lower-level trees. The upper-level trees handle OCV impact reduction, while the lower-level trees handle latency and power consumption optimization. This segmentation ensures that each level focuses on its specific optimization goal without compromising the other.
Solution Approach 2:
The patent applies different optimization qualities to different levels of the clock tree. The lower-level trees use optimization strategies tailored for minimizing latency and power consumption, while the upper-level trees use strategies for reducing OCV impact. This local quality approach allows each part to be optimized for its specific functional requirements.
Data Source
AI summary
Dual-structure clock tree synthesis (CTS) is described. Some embodiments can construct a set of upper-level clock trees, wherein each leaf of each upper-level clock tree is a root of a lower-level clock tree. Each upper-level clock tree can be optimized to reduce an impact of on-chip-variation and/or cross-corner variation on clock skew. Next, for each leaf of each upper-level clock tree, the embodiments can construct a lower-level clock tree to distribute a clock signal from the leaf of the upper-level clock tree to a set of clock sinks. The lower-level clock tree can be optimized to reduce latency, power consumption, and/or area.