Dual-Sub-ADC Architecture for High-Resolution Throughput Limits
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Solution Overview
Problem
High-resolution analog to digital converters (ADCs) using successive approximation techniques face low throughput due to their iterative nature, which becomes exacerbated with higher bit resolutions, leading to longer conversion times and potential noise issues.
Innovation Solution
Implementing a dual-sub-ADC architecture where one sub-ADC resolves bits in parallel mode and the other uses successive approximation with a charge redistribution DAC, allowing for simultaneous bit resolution and minimizing power consumption by eliminating charge leakage, thereby enhancing conversion speed and reducing noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If successive approximation technique is used to achieve high resolution conversion, then measurement precision is improved, but productivity deteriorates due to iterative conversion process
Solution Approach 1:
The ADC is divided into two independent sub-ADCs: a first sub-ADC that processes MSBs using successive approximation technique, and a second sub-ADC that processes LSBs using parallel comparison. This segmentation allows each sub-ADC to specialize in specific bit ranges, enabling high-resolution conversion while improving throughput through parallel operation of the second sub-ADC.
2Measurement precision
If iterative successive approximation is used for each bit position, then measurement precision is improved, but loss of time increases due to sequential processing
Solution Approach 1:
The first sub-ADC performs successive approximation conversion for the most significant bits first, establishing a preliminary digital code that represents the upper portion of the analog signal. This preliminary conversion result is then used by the second sub-ADC to perform parallel comparison for the remaining least significant bits, eliminating the need for iterative processing of all bits and reducing total conversion time.
3Manufacturing precision
If charge redistribution DAC is used in successive approximation ADC, then manufacturing precision is improved, but loss of energy occurs due to charge leakage
Solution Approach 1:
The charge redistribution DAC is extracted from the successive approximation ADC structure and placed only in the first sub-ADC that processes MSBs. The second sub-ADC that processes LSBs uses a different architecture (parallel comparison) that does not rely on charge redistribution, thereby eliminating the charge leakage problem and associated power consumption issues while maintaining conversion accuracy through the combined output of both sub-ADCs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves the throughput of high-resolution ADCs by resolving bits in parallel, reducing power consumption, and minimizing noise, enabling faster and more accurate digital code generation.
Implementation Method 1
containing a charge redistribution digital to analog converter (DAC)
Data Source
AI summary
An analog to digital converter (ADC) containing a sub-ADC to resolve at least some of the bits using successive approximation principle (SAP), while providing various improvements. According to one aspect, another sub-ADC is used to resolve some of the bits in parallel. According to another aspect, the sub-ADC using SAP is implemented using a charge redistribution principle, while another sub-ADC does not rely on charge conservation. According to yet another aspect of the present invention, a same component operates as a comparator when the sub-ADC using SAP resolves the corresponding bits, and operates as an amplifier when the sub-ADC generates a residue signal.