Semiconductor Memory Layout Using Dual Substrates and Vertical Lines
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Solution Overview
Problem
Current semiconductor devices face challenges in miniaturization, low power consumption, and high performance due to the complexity of integrating multiple memory cells and driving circuits within a limited area, which hinders their efficiency and functionality in electronic devices.
Innovation Solution
The semiconductor device incorporates a dual-substrate structure with vertically stacked word and bit lines, where each substrate has its own driving circuits, allowing for a hybrid bonding configuration that reduces the cell region area by overlapping driving circuits outside the cell region, thereby increasing the overlap between word and bit lines and enhancing memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple memory cells and driving circuits are integrated within a limited area, then device functionality is improved, but device area increases
Solution Approach 1:
The patent transitions from a planar integration approach to a three-dimensional stacked architecture. Multiple memory cell arrays are vertically stacked across different substrates (first substrate, second substrate, third substrate) and connected via through-substrate vias. This vertical stacking enables multiple memory cells to share the same footprint area, significantly increasing storage capacity per unit area while maintaining compact device dimensions.
Solution Approach 2:
The device is divided into multiple independent substrate layers (first substrate, second substrate, third substrate), each containing separate memory cell arrays and driving circuits. This segmentation allows parallel processing of multiple memory arrays, improving device functionality and performance while distributing the total circuit area across multiple layers rather than concentrating everything in a single plane.
2Productivity
If memory cell density is increased, then device performance is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages for each substrate layer. Each substrate can be fabricated, tested, and processed independently before being stacked with other substrates. This modular manufacturing approach enables high memory cell density to be achieved through repeated stacking of standardized units, rather than attempting to integrate everything in a single complex fabrication step.
Solution Approach 2:
Multiple complete memory subsystems (each consisting of memory cell arrays, word lines, bit lines, and driving circuits) are nested within one another across vertical layers. Each substrate contains a complete functional memory array that can be independently manufactured and then integrated into the final stacked device, simplifying the overall manufacturing process while achieving high density.
Data Source
AI summary
A semiconductor device may include: a first substrate structure including: a first substrate; a first word line, a first bit line, a second bit line, a second word line, a third word line, a third bit line, a fourth bit line, and a fourth word line that are sequentially arranged over the first substrate in a vertical direction; and first, second, third, and fourth memory cells, the first memory cell being disposed between the first word line and the first bit line, the second memory cell being disposed between the second word line and the second bit line, the third memory cell being disposed between the third word line and the third bit line, and the fourth memory cell being disposed between the fourth word line and the fourth bit line; and a second substrate structure disposed over the first substrate structure and including a second substrate.