Dual Substrate Power Module Assembly with Reduced Inductance
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Solution Overview
Problem
Power module assemblies face challenges in achieving high power density while minimizing parasitic inductance, which affects their ability to generate power and operate efficiently at high switching frequencies.
Innovation Solution
A power module assembly with dual substrates and a conductive joining layer is designed, where the first and third layers of the first substrate, combined with the fourth and sixth layers of the second substrate, form a unitary conducting layer to reduce net inductance by canceling switch current flowing in opposite directions, achieved through a sintering process that forms a silver joining layer between the substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional single-substrate power module assemblies are used, then manufacturing is simpler, but parasitic inductance is higher and power density is reduced
Solution Approach 1:
The power module assembly is divided into two separate substrates (first substrate with switch current path, second substrate with return current path) instead of using a single substrate. This segmentation allows the current paths to be optimized independently, reducing parasitic inductance while maintaining manageable manufacturing complexity through modular assembly.
Solution Approach 2:
The invention transitions from a planar single-substrate layout to a three-dimensional dual-substrate configuration stacked vertically and connected through conductive joining layers. This dimensional change enables shorter current paths and better current cancellation effects, reducing parasitic inductance while distributing components more efficiently in space.
2Power
If high power density is achieved through compact design, then power output increases, but parasitic inductance increases due to constrained current paths
Solution Approach 1:
By segmenting the current paths across two substrates, the invention enables compact high-power density design without compromising inductance performance. Each substrate handles specific current functions (switching and return), allowing dense component placement while maintaining optimized current paths that cancel magnetic fields and reduce parasitic inductance.
3Loss of energy
If switch current paths are lengthened to reduce inductance, then parasitic inductance decreases, but device area increases reducing power density
Solution Approach 1:
The invention uses vertical stacking of substrates connected by conductive joining layers to create short current paths in the vertical dimension, eliminating the need for long horizontal current paths. This three-dimensional arrangement reduces parasitic inductance while maintaining a compact footprint, thereby preserving high power density without requiring increased device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration supports high switching frequency operations, reduces parasitic inductance, and enhances power density, allowing for efficient energy transfer and reduced energy losses in semiconductor devices.
Implementation Method 1
The sintering process includes urging micro particles of a predefined metal to coalesce into a solid form via heating at a predetermined temperature for a predetermined time. The sintering process may include compressing the micro particles of the predefined metal between the first and second substrates at a predefined pressure.
Data Source
AI summary
A power module assembly has a first substrate including a first layer, second layer and a third layer. The first layer is configured to carry a switch current flowing in a first direction. A second substrate is operatively connected to the first substrate and includes a fourth layer, fifth layer and a sixth layer. A conductive joining layer connects the third layer of the first substrate and the fourth layer of the second substrate. The conductive joining layer may be a first sintered layer. The third layer of the first substrate, the first sintered layer and the fourth layer of the second substrate are configured to function together as a unitary conducting layer carrying the switch current in a second direction substantially opposite to the first direction. The net inductance is reduced by a cancellation effect of the switch current going in opposite directions.