Dual Sum Quadword Multiply Accumulate Instructions for Sensing
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Solution Overview
Problem
Current processor cores using multiplication integer instructions for dot product operations are not sufficiently fast and do not support the use of signed and unsigned values, which is a limitation in sensing applications that require efficient handling of signed and unsigned integer data types.
Innovation Solution
The introduction of the DVPDPWSUQ and DVPDPWUSQ instructions, which enable vector packed multiply and accumulate operations for both signed and unsigned data elements, allowing for efficient execution of dot product operations across multiple channels in sensing applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiplication integer instructions are used for dot product operations, then the operations can be performed with signed and unsigned values, but the processing speed is not sufficiently fast
Solution Approach 1:
The patent segments the dot product operation into distinct multiply and accumulate phases, allowing parallel processing of multiple data elements simultaneously. The execution unit is divided into separate multiplication and accumulation components that can operate concurrently on different elements, thereby increasing processing speed while maintaining support for both signed and unsigned integer types.
Solution Approach 2:
The patent introduces a new instruction format and execution unit architecture that adds a dimensional aspect to integer multiplication by incorporating dual-sum capability. This allows the processor to handle multiple accumulate results in parallel, effectively adding a processing dimension that increases throughput without sacrificing speed for individual operations.
2Adaptability or versatility
If standard multiplication instructions are used, then code can handle both signed and unsigned data types, but the code memory footprint increases
Solution Approach 1:
The patent creates a universal multiply-accumulate instruction that can handle both signed and unsigned integer data types within the same instruction format and execution unit. This multi-functional approach eliminates the need for separate instruction sequences for different data types, reducing code memory footprint while maintaining full adaptability to various sensing applications requiring different integer types.
Solution Approach 2:
The patent utilizes parameter changes in the instruction encoding to indicate whether signed or unsigned operations should be performed. By incorporating data type specification parameters within the instruction itself, the system can switch between handling signed and unsigned values without requiring different instruction formats or additional code, thereby reducing memory footprint while preserving versatility.
3Reliability
If multiple separate instructions are used for dot product operations, then each operation can be optimized, but the code complexity and memory usage increase
Solution Approach 1:
The patent merges the multiply and accumulate operations into a single unified instruction that performs both functions atomically. This combination maintains operational accuracy by ensuring proper ordering and timing of operations while significantly reducing code complexity. The unified instruction eliminates the need for multiple separate instructions, reducing both code size and the complexity of instruction sequencing required for dot product operations.
Solution Approach 2:
The patent incorporates preliminary setup of the execution unit state within the instruction itself, including configuration for signed or unsigned operation mode. This preliminary action within the single instruction eliminates the need for multiple preparatory instructions, reducing overall code complexity while maintaining reliable operation through proper initial state configuration before the actual compute operations begin.
Data Source
AI summary
Techniques for matrix multiplication are described. In some examples, a single instruction having a format of fields for an opcode, one or more fields to indicate a location of a source/destination operand, one or more fields to indicate a location of a first source operand, and one or more fields to indicate a location of a second source operand is used. Wherein the opcode is to indicate that execution circuitry is to: multiply values from corresponding data elements of the first and second sources, add a first subset of the multiplied values to a first value from the source/destination operand and store in a first data element position of the source/destination operand, and add a second subset of the multiplied values to a second value from the source/destination operand and store in a second data element position of the source/destination operand.