Dual-Supply Level Shifting Circuit Without Bias Voltage
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Solution Overview
Problem
Existing level shifting circuits fail to respond to reduced operating voltages and requests for lower power consumption and higher functionality, particularly in scenarios where circuits with different power supply voltages are involved.
Innovation Solution
A level shifting circuit design utilizing two power supplies and symmetric configurations of n-type and p-type transistors, along with resistors and buffers, to enhance the switching speed and eliminate the need for a bias voltage, thereby increasing the rising and falling speeds of output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional level shifting circuit configuration is used, then the voltage conversion function is achieved, but the circuit operation speed is slow and power consumption is high
Solution Approach 1:
The level shifting circuit is divided into two independent but symmetrical halves: one for converting low voltage to high voltage, and another for converting high voltage to low voltage. Each half contains dedicated transistors (first n-type, first p-type, second n-type, second p-type) and resistors that operate independently, allowing simultaneous bidirectional voltage conversion without interference, thereby increasing overall circuit operation speed
Solution Approach 2:
The patent employs asymmetric transistor configuration where n-type and p-type transistors are used in complementary pairs with different connectivity patterns. The n-type transistors have gates connected to the first power supply, while p-type transistors have gates connected to complementary signals, creating asymmetric switching characteristics that optimize both speed and power consumption for different voltage transition directions
2Reliability
If the voltage between Low and High levels is decreased to lightening voltage stress on transistors, then transistor reliability is improved, but the circuit fails to respond to reduced operating voltages and higher functionality requests
Solution Approach 1:
The circuit dynamically adjusts operating parameters by utilizing two different power supply voltages (first power supply and third power supply at higher potential). This allows the circuit to adapt to different voltage conditions and functionality requirements while maintaining transistor voltage stress within safe limits through the controlled voltage conversion process
Solution Approach 2:
The level shifting circuit is designed to perform multiple functions: it can convert low voltage to high voltage, high voltage to low voltage, and operates reliably across different voltage conditions. The symmetrical transistor configuration and dual power supply approach enable the circuit to handle various signal types and voltage levels, providing universal adaptability
3Speed
If a bias voltage circuit is added to improve switching performance, then signal transition speed is enhanced, but device complexity and power consumption increase
Solution Approach 1:
The circuit achieves fast signal transitions without external bias voltage by utilizing the inherent complementary switching action of the n-type and p-type transistor pairs. The transistors self-regulate their switching timing through their gate connections to complementary signals, eliminating the need for separate bias voltage generation circuits and reducing overall system complexity
Data Source
AI summary
A level shifting circuit includes first to sixth p-type transistors, first and second n-type transistors, and first and second resistors. The first p-type transistor and the first n-type transistor are provided between an input node and an output node. The second p-type transistor is provided between a third power supply and the output node. The third p-type transistor is provided between a first power supply and the output node. The first resistor is provided between a third node and the output node. The fourth p-type transistor and the second n-type transistor are provided between an inverted input node and an inverted output node. The fifth p-type transistor is provided between the third power supply and the inverted output node. The sixth p-type transistor is provided between the first power supply and the inverted output node. The second resistor is provided between a sixth node and the inverted output node.