Dual Supply Memory Cell with Independent Wordline Control
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Solution Overview
Problem
Existing SRAM cells face instability and operational limitations at low supply voltage levels, leading to read instability and restricted low voltage functionality due to local mismatch and the need for a stable memory cell configuration in integrated circuits.
Innovation Solution
Implementing a dual power supply system with a higher high supply voltage (Vddh) for memory cell inverters and wordline drivers, and a lower high supply voltage (Vddl) for bitline circuitry, allowing independent control of two wordlines for each memory cell to ensure stable operation at lower voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single power supply voltage is used for the memory cell, then the device complexity is reduced, but the memory cell stability deteriorates at low supply voltages
Solution Approach 1:
The power supply system is segmented into two independent voltage domains: a first high supply voltage (Vddh) for the memory cell inverters and wordline drivers, and a second high supply voltage (Vddl) for the bitline circuitry. This segmentation allows each subsystem to operate at its optimal voltage level, maintaining memory cell stability while enabling low-voltage operation of peripheral circuitry.
Solution Approach 2:
Different parts of the memory system are assigned different voltage characteristics: the memory cell core operates at the higher Vddh to ensure stability and meet the minimum voltage requirement Vdd(min), while the bitline circuitry operates at the lower Vddl to enable low-voltage functionality. This local quality differentiation resolves the contradiction between simplicity and stability.
2Use of energy by moving object
If the supply voltage is lowered to improve low voltage functionality, then energy consumption is reduced, but read instability increases
Solution Approach 1:
The system separates the voltage domains so that energy-efficient low-voltage operation (Vddl) is achieved in the bitline circuitry while the memory cell core maintains higher voltage (Vddh) for stable read operations. This segmentation allows the system to reduce overall energy consumption without compromising read stability.
Solution Approach 2:
The supply voltage parameter is changed differently for different subsystems: Vddh is maintained at or above Vdd(min) to ensure read stability, while Vddl is lowered to achieve low-voltage functionality and reduced energy consumption in peripheral circuitry. This parameter differentiation resolves the contradiction between energy efficiency and reliability.
3Device complexity
If a single wordline is used to control both access transistors, then the device complexity is reduced, but the control precision deteriorates
Solution Approach 1:
The wordline control is segmented into two independent wordlines: a first wordline (WL1) controlling the first access transistor and a second wordline (WL2) controlling the second access transistor. This segmentation enables precise independent control of each access transistor, improving read stability and preventing the harmful effect where simultaneous activation causes voltage rise that turns on the n-channel transistor and flips cell data.
Solution Approach 2:
The dual wordline configuration allows preliminary control of access transistor activation to prevent harmful effects. By controlling WL1 and WL2 independently, the system can activate access transistors in a controlled sequence or selectively, preventing the condition where both transistors are simultaneously on, which would cause read instability and data flipping.
Data Source
AI summary
A memory cell includes a latch having a true data node and a complement data node, a true bitline, a complement bitline, a first access transistor coupled between the true bitline and the true data node, and a second access transistor coupled between the complement bitline and the complement data node. A wordline driver circuit includes a true wordline coupled to control the first access transistor and a complement wordline coupled to control the second access transistor. The wordline driver generates control signals on the true and complement wordlines to access the memory cell by: actuating the first access transistor while the second access transistor is not actuated and then actuating the second access transistor while the first access transistor is not actuated. The bitlines and wordlines are supplied from different sets of power supply voltages, with the bitline high supply voltage being less than the wordline high supply voltage.