Dual-Supply Configuration Memory Cells for Deterministic Reset
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Solution Overview
Problem
Existing programmable logic devices face challenges in ensuring deterministic reset of configuration memory cells during power-up and reprogramming events, leading to potential contention and undesired behavior due to unpredictable initial states of memory cells.
Innovation Solution
Implementing dual power supply lines for configuration memory cells, where one line is decoupled during reset to ensure a known reset state, and using bitline signals to drive cells to a complementary state, facilitating a deterministic reset.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single power supply line is used for configuration memory cells, then the device complexity is reduced, but the reliability of reset operation deteriorates due to unpredictable initial states
Solution Approach 1:
The power supply system is segmented into two separate power supply lines (first power supply line and second power supply line) that can be independently controlled. This segmentation allows the first power supply line to be decoupled during reset operations while the second remains active, enabling deterministic reset of configuration memory cells without affecting overall device operation.
Solution Approach 2:
The power supply circuit incorporates dynamic control through a power supply circuit that can selectively couple and decouple the first power supply line based on reset control signals. This dynamic capability allows the system to transition between different power supply states (normal operation vs. reset) to achieve reliable memory cell initialization.
2Reliability
If power is continuously supplied to configuration memory cells, then the ease of operation is improved, but the reliability deteriorates due to potential contention during power-up and reprogramming events
Solution Approach 1:
The system performs preliminary action by decoupling the first power supply line before memory cell initialization occurs during reset operations. This preliminary decoupling prevents potential contention and ensures that memory cells start from a known reset state before configuration data is loaded, eliminating unpredictable behavior during power-up and reprogramming events.
3Manufacturing precision
If dual power supply lines are implemented with selective coupling, then the manufacturing precision of reset state is improved, but the device complexity increases due to additional power supply circuit requirements
Solution Approach 1:
The power supply circuit is designed with multi-functionality to perform both normal power supply operation and deterministic reset operations using the same circuit infrastructure. The circuit can selectively couple the first power supply line during normal operation and decouple it during reset operations, achieving dual functionality without requiring completely separate circuit systems.
Data Source
AI summary
Various techniques are provided to implement dual power supplied memory cells and deterministic reset thereof for programmable logic devices. In one example, a programmable logic device (PLD) includes a configuration memory including an array of memory cells arranged in rows and columns. The PLD further includes a power supply circuit coupled to the configuration memory and configured to selectively couple, based on a reset control signal, a power supply to a first power supply line coupled to the array of memory cells. The array of memory cells is reset if the power supply is coupled to the first power supply line. The power supply circuit is further configured to provide power on a second power supply line to the array of memory cells. Related methods and devices are provided.