Dual-Surface Memory Cell Layout for Higher DRAM Integration
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Solution Overview
Problem
There is an increasing demand for highly-integrated semiconductor memory devices with reduced linewidths and improved integration density and sensing margins, which existing technologies struggle to achieve.
Innovation Solution
The semiconductor memory device is designed with bit lines and capacitors formed on both surfaces of the substrate, allowing for increased integration density and process margins through a specific layout and fabrication process that includes alternating bit lines on opposite surfaces and capacitors on both surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit lines and capacitors are formed only on one surface of the substrate, then the fabrication process is simpler, but the integration density and sensing margins are insufficient
Solution Approach 1:
The patent extends the device structure from a single surface to both surfaces of the substrate. First bit lines are formed on the first surface, while second bit lines are formed on the second surface. Capacitors are also distributed on both surfaces, with first capacitors on the first surface and second capacitors on the second surface. This three-dimensional utilization of space increases integration density without proportionally increasing process complexity
Solution Approach 2:
The bit lines are segmented into first bit lines on the first surface and second bit lines on the second surface. Similarly, capacitors are segmented into first capacitors on the first surface and second capacitors on the second surface. This segmentation allows independent optimization of each surface's layout and reduces interference between components, enabling higher integration density
2Quantity of substance
If linewidths are reduced to increase integration density, then more components can be packed, but manufacturing precision requirements increase
Solution Approach 1:
By utilizing both surfaces of the substrate for bit line and capacitor formation, the patent effectively doubles the available area for component placement. This dimensional expansion allows maintenance of larger linewidths while achieving high integration density, thereby reducing manufacturing precision requirements compared to single-surface designs
3Reliability
If capacitors are placed on both surfaces of the substrate, then sensing margins are improved, but the device structure becomes more complex
Solution Approach 1:
The patent positions first capacitors on the first surface and second capacitors on the second surface, utilizing the third dimension (substrate thickness) to increase capacitor capacity and improve sensing margins. The alternating arrangement with bit lines provides structural regularity that manages complexity while maintaining reliability benefits
4Area of stationary object
If alternating bit lines are disposed in the first direction on opposite surfaces, then space utilization is optimized, but alignment precision requirements increase
Solution Approach 1:
The alternating arrangement of first and second bit lines in the first direction on opposite surfaces creates a regular, periodic structure that optimizes space utilization. This systematic alternation provides clear alignment references that can be managed with standard manufacturing precision, preventing excessive complexity despite the three-dimensional layout
Data Source
AI summary
A semiconductor memory device includes a substrate including active regions, the active regions having first impurity regions and second impurity regions, word lines on a first surface of the substrate, the word lines extending in a first direction, first bit lines on the word lines, the first bit lines extending in a second direction crossing the first direction, and the first bit lines being connected to the first impurity regions, first contact plugs between the first bit lines, the first contact plugs being connected to the second impurity regions, respectively, second bit lines on a second surface of the substrate, the second bit lines being electrically connected to the first impurity regions, and a first capacitor on the first contact plugs.