Dual-Surface MOS Transistor Architecture for Reduced On-Resistance
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Solution Overview
Problem
Trench type MOS transistors face limitations in reducing on-resistance and achieving higher current flow due to constraints in the density of trenches and gate electrodes per unit area.
Innovation Solution
A semiconductor device design featuring first and second MOS transistors on opposite surfaces of a substrate with shared drain and source electrodes, and penetration holes for wiring connections, allowing for increased channel density and reduced on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trenches and gate electrodes are increased in density to reduce on-resistance, then on-resistance decreases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent utilizes both the front surface and back surface of the semiconductor substrate to form MOS transistors, effectively transitioning from a two-dimensional single-surface configuration to a three-dimensional dual-surface configuration. This allows doubling the channel density per unit area without increasing the planar footprint, thereby reducing on-resistance without proportionally increasing device complexity
2Productivity
If more trenches and gate electrodes are formed per unit area, then current flow capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the MOS transistor formation into two separate segments: one set of transistors formed on the front surface and another set on the back surface. Each surface can be processed independently with optimized trench spacing and gate electrode dimensions, allowing standard manufacturing precision to achieve higher overall current capacity without requiring ultra-precise high-density single-surface fabrication
3Reliability
If the number of channels per unit area is doubled, then on-resistance is reduced, but device size increases
Solution Approach 1:
By forming MOS transistors on both the front and back surfaces of the semiconductor substrate, the patent effectively adds a third dimension (the substrate thickness direction) to the transistor placement. This allows doubling the channel count per unit planar area without increasing the device footprint, as the additional transistors occupy the opposite surface rather than expanding the lateral dimensions
Data Source
AI summary
The invention realizes low on-resistance and high current flow in a semiconductor device in which a current flows in a thickness direction of a semiconductor substrate. A first MOS transistor having first gate electrodes and first source layers is formed on a front surface of a semiconductor substrate, and a second MOS transistor having second gate electrodes and second source layers is formed on a back surface thereof. A drain electrode connected to the semiconductor substrate, a first source electrode connected to the first source layers, a second source electrode connected to the second source layers, and a first penetration hole penetrating the semiconductor substrate are further formed. A first wiring connecting the first source electrode and the second source electrode is formed in the first penetration hole. The semiconductor substrate serves as a common drain region of the first and second MOS transistors.