Dual-Surface MTJ Memory Layout for Integrated OTP Cells
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Magnetic memory devices face challenges in high integration and increased manufacturing costs due to the need for separate memory cell arrays for normal and one-time programmable (OTP) cells, which enlarges the write driver area.
Innovation Solution
A magnetic memory device design with vertically stacked active regions and magnetic tunnel junctions (MTJs) on both the front and back surfaces of the substrate, integrating MTJs in both reversible and irreversible states, and using through-contact plugs and backside wiring to optimize electrical connectivity and reduce wiring complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate memory cell arrays are used for normal and OTP cells, then reliability is improved by preventing high voltage from affecting normal cells, but device complexity increases and manufacturing cost increases
Solution Approach 1:
The patent divides the memory device into distinct front surface and back surface regions. Normal MTJ cells are positioned on the front surface while OTP cells are positioned on the back surface, physically segmenting the high voltage protection function from the normal cell array. This segmentation allows independent operation and protection schemes for each cell type.
Solution Approach 2:
The patent extracts the OTP cell functionality from the main normal cell array and places it in a separate back surface array. This extraction eliminates the need for complex isolation structures within the main array while maintaining high voltage protection. The OTP cells are taken out and positioned where they can access high voltage without interfering with normal cell operations.
2Reliability
If separate memory cell arrays are used for normal and OTP cells, then reliability is improved by preventing high voltage from affecting normal cells, but manufacturing cost increases
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional configuration by utilizing both front and back surfaces of the substrate. This dimensional change allows normal and OTP cells to coexist without requiring separate fabrication processes or additional wafer layers, thereby reducing manufacturing complexity and cost while maintaining reliable high voltage isolation.
3Area of moving object
If vertically stacked active regions are used, then integration is increased and area is reduced, but wiring complexity increases
Solution Approach 1:
The patent inverts the conventional wiring approach by placing active contacts on the back surface of the substrate rather than only on the front surface. This inversion allows wiring to be routed through the substrate thickness, reducing the need for complex multi-layer interconnect structures and simplifying the overall wiring architecture while maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves increased integration, reduced wiring complexity, and lower manufacturing costs while maintaining high-speed and non-volatile memory operations, eliminating the need for separate OTP memory arrays.
Implementation Method 1
A resistance associated with the magnetic tunnel junction pattern may be changed based at least in part upon magnetization directions of the two magnetic layers. For example, when the magnetization directions of the two magnetic layers are anti-parallel to each other, the magnetic tunnel junction pattern may have a high resistance. When the magnetization directions of the two magnetic layers are parallel to each other, the magnetic tunnel junction pattern may have a low resistance.
Implementation Method 2
The tunnel barrier pattern of the first magnetic tunnel junction pattern is insulated-broken and has an irreversible resistance state
Data Source
AI summary
A magnetic memory device includes: a substrate having upper and lower surfaces; a first active region on the upper surface of the substrate, and including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern; a second active region on the first active region, and including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern; an interlayer insulating layer covering the lower and upper source/drain patterns; a first active contact on the upper source/drain pattern; an upper insulating layer disposed on the interlayer insulating layer; a first magnetic tunnel junction pattern in the upper insulating layer, and connected to the first active contact; a backside wiring layer on the lower surface of the substrate; a second magnetic tunnel junction pattern in the backside wiring layer; and a second active contact on the lower source/drain pattern.