Dual-Surface Electronic Package for Miniaturization
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Solution Overview
Problem
Conventional semiconductor packages face challenges in miniaturization due to the large surface area occupied by semiconductor chips and passive elements, hindering the reduction of overall volume and hindering the integration of high-speed communication technologies in electronic products.
Innovation Solution
The solution involves a dual-layer electronic package structure where first and second electronic elements are disposed on opposite surfaces of a substrate, with a frame bonded to one surface and encapsulants on both surfaces to maintain miniaturization without increasing volume, while also providing protection against moisture, pollutants, and electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor chips and passive elements are disposed on a single surface of the substrate, then the electrical performance is improved, but the surface area occupied increases, leading to increased package volume
Solution Approach 1:
The patent transitions from a two-dimensional single-surface arrangement to a three-dimensional dual-surface configuration by disposing first electronic elements on the first surface and second electronic elements on the second surface of the substrate, effectively utilizing the vertical dimension to reduce the occupied surface area while maintaining high electrical performance
Solution Approach 2:
The patent segments the electronic elements into two groups (first electronic elements and second electronic elements) and distributes them on opposite surfaces of the substrate, with each group encapsulated by separate encapsulants, thereby reducing the surface area requirement for each individual element while maintaining overall functionality
2Quantity of substance
If the surface area of the substrate is increased to accommodate more electronic elements, then the integration density is improved, but the overall volume of the package increases
Solution Approach 1:
The patent utilizes the third dimension (vertical depth) by implementing a dual-surface configuration with first electronic elements on the first surface and second electronic elements on the second surface, allowing increased element quantity without increasing the horizontal footprint or overall package volume
Solution Approach 2:
The patent employs nested encapsulation structures where first and second encapsulants are formed on opposite surfaces of the substrate, creating a protective enclosure that accommodates multiple electronic elements within a compact volume without requiring additional package space
3Ease of manufacture
If electronic elements are exposed without encapsulation, then the manufacturing process is simplified, but the protection against moisture and pollutants is reduced
Solution Approach 1:
The patent applies preliminary protective action by forming first and second encapsulants on the electronic elements before final assembly completion, creating a protective barrier against moisture and pollutants that ensures long-term reliability without complicating the manufacturing process
Solution Approach 2:
The patent utilizes encapsulants as protective thin film structures that envelop the electronic elements on both surfaces of the substrate, providing effective protection against environmental harmful factors while maintaining a compact and integrated package structure
4Device complexity
If a single-layer encapsulant structure is used, then the manufacturing complexity is reduced, but the impact resistance and cracking resistance are insufficient
Solution Approach 1:
The patent implements a composite encapsulation structure with first and second encapsulants formed on opposite surfaces of the substrate, creating a multi-layer protective system that enhances impact resistance and cracking resistance through distributed stress absorption while maintaining manufacturing feasibility
Solution Approach 2:
The patent applies beforehand cushioning by forming protective encapsulants on both surfaces of the substrate that absorb and distribute mechanical stresses before they can cause damage to the electronic elements, thereby enhancing impact and cracking resistance in advance
Data Source
AI summary
An electronic package is provided, including: a substrate having opposite first and second surfaces; at least a first electronic element disposed on the first surface of the substrate; a first encapsulant encapsulating the first electronic element; at least a second electronic element and a frame disposed on the second surface of the substrate; and a second encapsulant encapsulating the second electronic element. By disposing the first and second electronic elements on the first and second surfaces of the substrate, respectively, the invention allows a required number of electronic elements to be mounted on the substrate without the need to increase the surface area of the substrate. Since the volume of the electronic package does not increase, the electronic package meets the miniaturization requirement. The present invention further provides a method for fabricating the electronic package.