Dual-Surface Power Semiconductor Mounting for Heat Dissipation

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Solution Overview

Problem

Existing electronic devices with power semiconductor chips face challenges in efficient mounting and cooling, leading to heat dissipation issues and reduced stability in high-frequency switching applications.

Innovation Solution

The development of electronic devices with two mounting surfaces, utilizing a leadframe or electrochemical deposition methods to integrate power semiconductor chips, along with external contact elements and insulating layers, allows for efficient electrical and thermal coupling to circuit boards, enabling effective heat dissipation and stable operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If power semiconductor chips are integrated into electronic devices with single mounting surface, then device structure is simple, but heat dissipation efficiency is poor and stability is reduced in high-frequency switching applications

Engineering Contradiction:
Improveheat dissipation efficiencyVSAvoiddevice structure
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent transitions from a single mounting surface configuration to a dual mounting surface configuration, adding a dimensional aspect to the device structure. This allows the power semiconductor chip to be mounted on both the first and second mounting surfaces, creating a three-dimensional thermal management architecture that improves heat dissipation efficiency while maintaining reasonable structural complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The device is segmented into two separate mounting surfaces (first mounting surface and second mounting surface) that can be independently configured and mounted on different substrates. This segmentation allows optimized thermal pathways and electrical connections on each surface, addressing the heat dissipation issue without requiring complete redesign of the entire device structure

Inventive Principle:
Principle #1Segmentation

2Reliability

If power semiconductor chips are integrated into electronic devices with single mounting surface, then manufacturing process is simple, but electrical connectivity and thermal management are insufficient

Engineering Contradiction:
Improvestability in high-frequency switching applicationsVSAvoidmanufacturing process
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The dual mounting surface configuration serves multiple functions simultaneously: the first mounting surface provides electrical connectivity and mechanical support, while the second mounting surface provides enhanced thermal management and additional electrical connections. This multi-functionality improves reliability in high-frequency switching applications without requiring entirely separate systems for each function

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces intermediate structures including insulating layers, conductive adhesives, and substrate materials that mediate between the power semiconductor chip and the mounting surfaces. These intermediaries enable improved electrical connectivity and thermal management while maintaining manufacturability through established fabrication techniques

Inventive Principle:
Principle #24Intermediary (Mediator)

3Use of energy by moving object

If traditional single mounting surface configuration is used, then device structure is simple, but thermal management efficiency is poor

Engineering Contradiction:
Improvethermal management efficiencyVSAvoidmounting structure
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent applies different properties and configurations to different regions of the mounting structure. The first mounting surface and second mounting surface have distinct characteristics optimized for their specific functions, with local variations in material composition, thickness, and connectivity patterns that enhance overall thermal management efficiency

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The mounting structure utilizes composite materials combining different thermal and electrical conductivity properties. Insulating layers with specific dielectric constants are combined with highly conductive thermal pathways, creating a composite structure that optimizes both thermal management and electrical performance without excessive complexity

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enhances the thermal management and electrical connectivity of power semiconductor chips, improving the stability and efficiency of high-frequency switching operations in electronic devices.

Implementation Method 1

utilizing a leadframe or electrochemical deposition methods to integrate power semiconductor chips

Methodology Applied
Scientific EffectElectrochemical deposition: Electrodeposition

Implementation Method 2

enabling effective heat dissipation and stable operation

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS8691631B2Device including two mounting surfaces
Publication Date: 2014.04.08 INFINEON TECHNOLOGIES AG
  • US8691631B2 patent drawing
  • US8691631B2 patent drawing
  • US8691631B2 patent drawing

AI summary

A device including two mounting surfaces. One embodiment provides a power semiconductor chip and having a first electrode on a first surface and a second electrode on a second surface opposite to the first surface. A first external contact element and a second external contact element, are both electrically coupled to the first electrode of the semiconductor chip. A third external contact element and a fourth external contact element, both electrically coupled to the second electrode of the semiconductor chip. A first mounting surface is provided on which the first and third external contact elements are disposed. A second mounting surface is provided on which the second and fourth external contact elements are disposed.