Dual-Surface Wiring for Floating-Body Multi-Gate Transistors
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Solution Overview
Problem
Current semiconductor apparatus designs limit the density and design flexibility of signal lines and power supply lines, as they are typically formed on either the upper or lower surface of the transistor element layer, restricting the formation of contacts and increasing parasitic resistance.
Innovation Solution
The semiconductor apparatus features a dual-layer wiring structure with the first wiring layer on one surface and the second wiring layer on the other, allowing for enhanced signal line density and design freedom, with both layers capable of forming contacts to transistors, thereby improving connectivity and reducing parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If signal lines and power supply lines are formed on a single surface of the transistor element layer, then the structure is simpler, but the line density and design flexibility are limited
Solution Approach 1:
The patent transitions from a two-dimensional single-surface wiring layout to a three-dimensional dual-surface wiring architecture. By utilizing both the upper and lower surfaces of the transistor element layer for wiring formation, the available wiring space is effectively doubled, thereby increasing signal line density and design flexibility without proportionally increasing structural complexity
2Ease of manufacture
If contacts are formed only from one surface, then the manufacturing process is simpler, but parasitic resistance increases
Solution Approach 1:
The contact formation process is segmented into two independent pathways: one from the upper surface and one from the lower surface. This segmentation allows each contact path to be optimized independently and enables parallel processing during manufacturing, while simultaneously reducing the length and resistance of each individual contact path by utilizing the shorter distance from the nearest surface
3Quantity of substance
If power supply wirings are embedded in the transistor element layer, then the wiring density is improved, but the manufacturing precision requirements increase
Solution Approach 1:
Instead of embedding all wirings within the transistor element layer, the patent utilizes the third dimension by extending wiring formation to both upper and lower surfaces. This dimensional expansion allows power supply wirings to be distributed across multiple layers and surfaces, reducing the density requirement within any single embedded layer while maintaining overall high wiring density through spatial distribution
Data Source
AI summary
To provide a semiconductor apparatus including a transistor element layer having a plurality of transistors which are multi-gate transistors of a floating body structure, a first wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least one pair of transistors among the plurality of transistors, the first wiring layer being laminated on the side of one surface of the transistor element layer, and a second wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least another pair of transistors among the plurality of transistors, the second wiring layer being laminated on the side of another surface of the transistor element layer.