Dual Sync Bus Clock Layout for Low-Skew Node Synchronization
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Solution Overview
Problem
Current synchronous clock systems face challenges in coordinating clock signals across multiple components and boards, leading to issues like increased jitter, noise, and reduced reliability due to propagation delays and impedance mismatches, while asynchronous systems sacrifice high performance for scalability and redundancy.
Innovation Solution
A synchronized clock system with two isolated synchronization busses and alternating connections of SXO modules, each with Synch IN and OUT terminals, spaced roughly equidistantly, providing redundancy and minimizing phase synchronization and skew issues through signal conditioning and recursive filtering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common clock signal is fanned out to each component, then clock distribution is simplified, but skew and jitter increase
Solution Approach 1:
The system divides the clock distribution into two separate synchronized busses (A and B) instead of one complex distribution network. Each bus carries clock signals to specific subsets of components, segmenting the overall distribution task to reduce skew and improve synchronization reliability.
Solution Approach 2:
The system changes the frequency parameter of the clock signal by using divide-by-2 logic at each SXO module. This frequency division reduces the clock rate, which in turn reduces jitter and allows for more reliable synchronization across distributed components.
2Reliability
If PLLs are used to eliminate skew, then synchronization is improved, but jitter increases
Solution Approach 1:
The system extracts and eliminates the need for PLLs entirely by using a different approach: two isolated synchronized busses with alternating SXO module connections. This removes the jitter-generating PLL components while maintaining phase synchronization through the bus architecture.
Solution Approach 2:
The synchronized busses act as intermediaries between clock sources and components, providing a clean transmission path that doesn't require active PLL correction. The bus structure itself provides the synchronization mechanism without introducing the harmful jitter that PLLs create.
3Speed
If clock multiplication is used to achieve data rate, then speed is improved, but jitter increases
Solution Approach 1:
Instead of multiplying a low-frequency clock to achieve data rate (which amplifies jitter), the system inverts the approach by using divide-by-2 logic to generate the clock from a higher-frequency source. This frequency division rather than multiplication prevents jitter amplification while still achieving the required data rates.
4Reliability
If SXO modules are connected in alternating fashion to two isolated busses, then redundancy and signal integrity are improved, but device complexity increases
Solution Approach 1:
The system merges the functionality of multiple clock distribution paths into two standardized synchronized busses. By alternating connections of SXO modules to these two busses, the system achieves redundancy and fault tolerance while maintaining a relatively simple standardized interface structure that can be systematically expanded.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system achieves minimal skew and phase noise, ensures reliable synchronization across multiple nodes, and maintains high performance with redundancy and signal integrity, allowing for scalable and fault-tolerant clock distribution.
Implementation Method 1
crystal oscillator-based clock
Data Source
AI summary
A synchronized clock system, for use with an electronic system having several system nodes requiring a synchronized clock signal. The clock system may be formed in either discrete form or in integrated form, or in any combination, and includes a first synch bus and a second synch bus, isolated from the first synch bus, and at least one pair and preferably several pairs of SXO modules connected to the busses in alternating fashion. Each of the system nodes is connected at a different one of any number of arbitrarily selected connection points anywhere along the first bus. The points along the busses at which the SXO modules are connected are spaced roughly equidistantly apart. The system nodes are connected to the bus by means of signal conditioning circuits, which may include correction circuits, an amplifier, a frequency multiplier, a logic translator and a fan buffer.