Dual Synchronizer Output Voting for Soft Error Mitigation
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Solution Overview
Problem
As device geometries shrink, synchronizer flip-flops become more susceptible to soft errors from cosmic radiation and power supply noise, leading to faults in digital systems, especially in safety-critical applications where these errors cannot be ignored.
Innovation Solution
A synchronizer circuit is designed with two parallel synchronizers and selection circuitry that compares their outputs, ensuring the output changes only if both agree, and uses stored values if they differ, thereby reducing or eliminating errors caused by soft errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device geometries are shrunk to increase integration density, then productivity and device density are improved, but soft error susceptibility increases due to cosmic radiation and power supply noise
Solution Approach 1:
The synchronizer is divided into two parallel synchronizer circuits (first synchronizer and second synchronizer) that operate independently. Each synchronizer processes the asynchronous input signal separately, and their outputs are compared by selection circuitry. This segmentation allows the system to maintain high integration density while improving reliability through redundant processing paths that can detect and correct soft errors.
2Reliability
If a single synchronizer is used, then device complexity is low, but reliability is reduced due to vulnerability to soft errors
Solution Approach 1:
A second synchronizer circuit is created as a copy of the first synchronizer, with identical structure and functionality. This copy is used to generate a redundant output signal that can be compared with the original synchronizer's output. The copying approach enables error detection through comparison while maintaining relatively simple individual synchronizer designs, balancing reliability improvement with device complexity.
3Reliability
If parallel synchronizers with comparison circuitry are added, then reliability is improved through error detection, but device complexity increases
Solution Approach 1:
The selection circuitry dynamically selects between the outputs of the first and second synchronizers based on real-time comparison results. When the outputs match, the system operates normally; when they differ, the selection circuitry identifies and selects the correct output. This dynamic adaptation enables the system to handle soft errors automatically without requiring complex static error correction mechanisms, balancing fault tolerance with circuit simplicity.
Data Source
AI summary
A synchronization circuit includes a first synchronizer, a second synchronizer, and selection circuitry. The first synchronizer is configured to synchronize a received signal to a clock signal. The second synchronizer is disposed in parallel with the first synchronizer and configured to synchronize the received signal to the clock signal. The selection circuitry is coupled to the first synchronizer and the second synchronizer. The selection circuitry is configured to provide an output value generated by the first synchronizer at an output terminal of the synchronization circuit based on the output value generated by the first synchronizer being the same as an output value generated by the second synchronizer.