Dual System Server With CPLD-Mediated BMC Coordination
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Solution Overview
Problem
Current dual socket servers are costly and prone to failure if one socket malfunctions, leading to system instability.
Innovation Solution
A dual system server design incorporating a central processing unit connected to two baseboard management controllers via PCIe interfaces, with a complex programmable logic device managing I2C interfaces to ensure functionality and fan operation even if one interface fails, and utilizing shared connectors and hard drives to reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual socket servers are used to improve system functionality, then the server can perform more tasks, but the cost increases and reliability decreases because the entire system fails if one socket malfunctions
Solution Approach 1:
The patent divides the dual-socket system into two independent one-socket systems, each with its own management controller. This segmentation allows each system to operate independently, so a failure in one socket does not cause the entire system to fail, thereby improving reliability while maintaining dual-system functionality.
Solution Approach 2:
The complex programmable logic device (CPLD) acts as an intermediary between the two baseboard management controllers, enabling communication and coordination between the two independent systems. This mediator allows the systems to work together while maintaining independence, resolving the contradiction between functionality and reliability.
2Adaptability or versatility
If dual socket servers are used to enhance system capabilities, then more processing power is available, but the manufacturing cost increases
Solution Approach 1:
The patent segments the dual-socket architecture into two separate one-socket configurations sharing a common motherboard. This approach allows manufacturers to use standard one-socket components and assembly processes, reducing manufacturing costs while still providing dual-system processing capabilities through the shared platform.
Solution Approach 2:
The common motherboard is designed to support two independent one-socket systems universally, allowing the same hardware platform to serve multiple functions. This multi-functionality reduces the need for specialized dual-socket manufacturing, thereby lowering costs while maintaining enhanced processing capabilities.
3Ease of manufacture
If two separate one-socket servers are placed on one mainboard to reduce cost, then manufacturing cost decreases, but system complexity increases
Solution Approach 1:
The CPLD serves as an intermediary that manages communication between the two baseboard management controllers and the central processing unit. This single mediator component simplifies the overall system architecture compared to having fully independent servers, reducing complexity while maintaining cost advantages of the shared motherboard approach.
Solution Approach 2:
The patent merges two one-socket servers onto a single motherboard, sharing common resources such as the chassis, power supply, and I/O interfaces. This consolidation reduces the total component count and assembly complexity compared to two separate servers, while still providing dual-system functionality.
Data Source
AI summary
A dual system server includes: a central processing unit, a first baseboard management controller, a second baseboard management controller and a complex programmable logic device. The first baseboard management controller is connected to the central processing unit through a first peripheral component interconnect express interface. The second baseboard management controller is connected to the central processing unit through a second peripheral component interconnect express interface. The complex programmable logic device is connected to the first baseboard management controller through a first inter-integrated circuit interface, and is connected to the second baseboard management controller through a second inter-integrated circuit interface.