Dual-Tail Latch Topology for Wide Input Common-Mode Sensing
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Solution Overview
Problem
Conventional dual-tail latches with either n-type or p-type input transistors face difficulties in sensing and latching data with wide input swings, leading to distortion of the data eye and reduced margin in systems with rail-to-rail input voltage, as the transistors often operate in the cut-off region.
Innovation Solution
A dual-component sensing stage is introduced, comprising a primary sensing stage and a complementary sensing stage with transistors of opposite types, operating in parallel to ensure accurate capture and amplification of input signals across a wide common mode range, thereby reducing the impact of transistors entering the cut-off region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional dual-tail latch uses single-type input transistors (n-type or p-type), then the circuit structure is simple, but the input common mode range is limited and transistors operate in cut-off region with wide input swings
Solution Approach 1:
The sensing stage is segmented into two parallel paths: one using n-type input transistors and another using p-type input transistors. Each path handles a specific portion of the input common mode range, allowing the overall circuit to accommodate wide input swings without transistors entering the cut-off region.
Solution Approach 2:
The invention uses a composite transistor structure combining both n-type and p-type input transistors in parallel. This composite approach allows the circuit to leverage the complementary characteristics of both transistor types, extending the effective input common mode range beyond what either transistor type could achieve alone.
2Ease of manufacture
If conventional dual-tail latch uses single-type input transistors, then manufacturing is easier, but data eye distortion occurs with rail-to-rail input voltage
Solution Approach 1:
By dividing the sensing function into two parallel segments (n-type path and p-type path), each segment can be optimized for its specific operating range. This segmentation prevents data eye distortion by ensuring that at least one path remains in its optimal operating region across the entire input voltage range.
Solution Approach 2:
Different transistor types are assigned to different operational regions: n-type transistors handle lower voltage ranges while p-type transistors handle higher voltage ranges. This local optimization ensures that each transistor operates in its optimal region, maintaining data eye symmetry and preventing distortion throughout the rail-to-rail input range.
3Device complexity
If conventional dual-tail latch uses single-type input transistors, then the design is straightforward, but RMT margin and DFE training performance are reduced
Solution Approach 1:
The parallel n-type and p-type transistor paths provide redundant sensing capability, increasing reliability. When one path approaches its operating limits, the other path continues to function effectively, thereby improving RMT margin and maintaining robust DFE training performance across varying input conditions.
Solution Approach 2:
The invention changes the operational parameters by introducing complementary transistor types with different threshold voltages and transconductance characteristics. This parameter diversification allows the circuit to maintain optimal performance across a wider range of input voltages, improving reliability metrics such as RMT margin without significantly increasing design complexity.
Data Source
AI summary
A memory device including an interface to receive one or more clock signals and one or more data signal a dual-sensing stage dual-tail latch arranged at the interface. The dual-sensing stage dual-tail latch includes a sensing stage to sense a differential voltage between a first signal and a second signal and to provide a first differential voltage output and a second differential voltage output to a first node and a second node, respectively. The dual-sensing stage dual-tail latch includes a complimentary sensing stage arranged in parallel with the sensing stage and to sense the differential voltage between the first signal and the second signal, where a first complimentary differential output voltage and a second complimentary differential output of the complimentary sensing stage are coupled to the first node and the second node. The dual-sensing stage dual-tail latch includes a latch stage to receive the outputs from the first node and the second node.