Dual Time-to-Digital Conversion for High-Speed Clock Recovery
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Solution Overview
Problem
Conventional clock and data recovery circuits face challenges in high-speed operations due to deteriorated jitter characteristics and complexity, particularly with the mixture of digital and analog circuits, leading to increased chip area and difficulty in recovering clock signals and data.
Innovation Solution
A time-to-digital conversion circuit is introduced, which includes first and second time-to-digital conversion circuits to compare phase differences between input and recovery clock signals, enabling easy recovery of clock and data by generating recovery clock and data signals, and simplifying the circuit configuration by using digital circuits only.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common clock and data recovery circuit with bang-bang phase detector is used, then the circuit can recover clock signal and data, but the jitter characteristic deteriorates in high-speed operation
Solution Approach 1:
The patent changes the operating parameters by introducing a time-to-digital conversion mechanism that measures phase difference in time units (UI - Unit Interval) rather than using traditional analog phase detection. This allows the circuit to maintain accurate phase measurement even at high data transmission speeds where traditional bang-bang phase detectors suffer from jitter deterioration.
2Reliability
If a common clock and data recovery circuit with mixed digital and analog circuits is used, then the circuit can recover clock signal and data, but the circuit configuration becomes complicated
Solution Approach 1:
The patent replaces the analog phase detection mechanism with a fully digital time-to-digital conversion system. Instead of using analog circuits to detect phase differences, the invention uses digital logic circuits that count clock cycles and calculate phase difference in time units, thereby simplifying the circuit configuration while maintaining recovery functionality.
3Reliability
If a common clock and data recovery circuit with passive elements is used, then the circuit can recover clock signal and data, but the chip area is increased
Solution Approach 1:
The patent eliminates passive elements (such as resistors, capacitors, and inductors) by replacing analog phase detection with digital time-to-digital conversion. The digital implementation uses only active logic elements, significantly reducing the chip area required for the clock and data recovery circuit while preserving its essential function.
4Speed
If a time-to-digital conversion circuit is used to compare phase differences, then the clock and data can be easily recovered at high speed, but the circuit requires digital-only implementation
Solution Approach 1:
The patent changes the fundamental measurement parameter from analog voltage/phase to digital time units. By measuring phase difference in terms of UI (Unit Interval) through digital counting and calculation, the circuit achieves high-speed operation capability while using only digital logic elements, making the implementation scalable and process-compatible.
Data Source
AI summary
The present disclosure discloses a time-to-digital conversion circuit for a clock and data recovery circuit. The time-to-digital conversion circuit may include a first time-to-digital conversion circuit enabled when a phase difference between a clock of an input signal and a recovery clock signal is greater than a reference phase difference and configured to output a first digital signal corresponding to the phase difference, and a second time-to-digital conversion circuit enabled when the phase difference is equal to or smaller than the reference phase difference and configured to output a second digital signal corresponding to the phase difference.