Dual-Semiconductor TFT Layout for Narrow-Bezel Displays
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Solution Overview
Problem
The challenge in display apparatus technology is to reduce power consumption while maintaining precise control over light emission, particularly in highly integrated display devices, where the number of thin-film transistors (TFTs) connected to each display element has increased, and there is a need to minimize the non-display area to enhance the display area size.
Innovation Solution
The solution involves a display apparatus with a combination of silicon and oxide semiconductor thin-film transistors, along with a specific arrangement of voltage lines and connection wires that bypass through the display area, reducing the non-display area by integrating the connection wires within the display area, thereby optimizing the layout and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of TFTs electrically connected to one display element is increased to precisely control light emission, then light emission control precision is improved, but power consumption increases
Solution Approach 1:
The patent changes the material parameter of TFTs from conventional single-type to dual-type (silicon-based and oxide semiconductor-based TFTs). The oxide semiconductor TFTs exhibit lower off-state current and lower power consumption characteristics, while maintaining the required light emission control precision through appropriate TFT selection and configuration in the pixel circuit.
2Reliability
If connection wires are arranged outside the display area to ensure proper electrical connections, then connection reliability is improved, but the non-display area increases reducing the display area size
Solution Approach 1:
The patent utilizes the third dimension (vertical stacking) by arranging connection wires in different layers above and below the display element. This allows connection wires to pass through the display area without occupying lateral space, thereby maintaining connection reliability while minimizing the non-display area and maximizing the display area size.
Solution Approach 2:
The patent nests connection wires within the display area by routing them through multiple layers and positions, effectively hiding them within the existing structure. The connection wires are integrated into the display stack, passing through or around display elements without requiring additional lateral space, thus reducing the non-display area while ensuring proper electrical connections.
Data Source
AI summary
A display apparatus is provided including a display area and a non-display area. The display area includes a display element and the non-display area includes a pad portion. A first thin-film transistor (TFT) is arranged in the display area. The first TFT includes silicon and a first gate electrode. A second TFT is arranged on a first insulating layer covering the first gate electrode and includes an oxide and a second gate electrode. A first voltage line extends in a first direction. A data line is spaced apart from the first voltage line. A connection wire is disposed in the display area and connects the data line to the pad portion. The connection wire includes a first portion extending in the first direction and a second portion extending in a second direction crossing the first direction, and the first portion overlaps the first voltage line.