Dual-Thickness Metal Silicide Gate Structure for Leakage Control
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Solution Overview
Problem
Highly integrated semiconductor devices face challenges in achieving low resistance and optimal operational characteristics due to the high resistance of polysilicon conductive patterns and excessive silicidation leading to increased junction leakage currents and reduced breakdown voltage.
Innovation Solution
A semiconductor device with a gate structure featuring a first metal silicide layer of specific thickness and a second metal silicide layer on impurity regions, where the second layer's thickness is controlled to be thinner than the first, preventing expansion into the channel region and allowing for separate control of silicide formation on different regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick metal silicide layer is formed on the polysilicon layer pattern to reduce gate electrode resistance, then the gate electrode resistance is reduced, but the metal silicide layer expands into the channel region causing increased junction leakage current and reduced breakdown voltage
Solution Approach 1:
The invention divides the silicidation process into two separate stages: first forming a thick metal silicide layer on the gate electrode for low resistance, then selectively removing metal from the channel region and re-siliciding only the source/drain regions. This segmentation allows independent optimization of gate resistance and channel protection.
Solution Approach 2:
The invention applies different metal silicide layer thicknesses to different regions: a thicker first metal silicide layer on the gate electrode for low resistance, and a thinner second metal silicide layer on the source/drain regions to prevent channel expansion. This local differentiation resolves the contradiction between low resistance and leakage prevention.
2Reliability
If a thick metal silicide layer is formed on the polysilicon layer pattern to reduce gate electrode resistance, then the gate electrode resistance is reduced, but the breakdown voltage is reduced due to metal silicide expansion into the channel region
Solution Approach 1:
The silicidation process is segmented into two stages with selective metal removal. The first stage forms thick silicide on the gate for low resistance, while the second stage forms thin silicide only on source/drain regions, preventing channel region expansion that would reduce breakdown voltage.
Solution Approach 2:
Different regions receive different metal silicide thicknesses: thick layer on gate electrode for conductivity, thin layer on source/drain for protection without channel expansion. This maintains high breakdown voltage while achieving low gate resistance.
3Reliability
If increasingly higher concentrations of impurities are introduced into the channel region to suppress short channel effect, then the short channel effect is suppressed, but abnormal tunneling currents increase
Solution Approach 1:
The invention changes the impurity concentration parameter in the channel region by forming a graded impurity profile through selective silicidation. The metal silicide layer on source/drain regions creates a gradual transition zone that suppresses short channel effect while minimizing tunneling current compared to abrupt high-concentration doping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces junction leakage currents, maintains low resistance, and enhances breakdown voltage, enabling the formation of transistors with desired characteristics in various regions of the semiconductor device.
Implementation Method 1
A thermal treatment is then carried out to drive a reaction between a metal in the metal layer and silicon in the polysilicon layer pattern and the source/drain regions
Data Source
AI summary
A semiconductor device includes a gate structure formed on a substrate. The gate structure includes an uppermost first metal silicide layer pattern having a first thickness. Spacers are formed on sidewalls of the gate structure. One or more impurity regions are formed in the substrate adjacent to at least one sidewall of the gate structure. A second metal silicide layer pattern, having a second thickness thinner than the first thickness, is formed on the one or more impurity regions.