Dual-Threshold Data Latch for Metastability-Resistant Clock Crossing
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Solution Overview
Problem
Conventional data storage elements for clock-domain crossing in digital applications face challenges with metastability and high failure rates due to the need for multiple flip-flops at high clock frequencies, leading to increased circuit area and complexity.
Innovation Solution
A data storage element design that generates an output signal based on two distinct threshold levels, using a master stage with two latches and an error stage to evaluate logical signals and set the output value only when both signals have the same state, reducing metastable states and circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FIFO interfaces or asynchronous interfaces with serially coupled flip flops are used for data exchanges between different clock domains, then the mean time between failures (MTBF) can be reduced, but the device complexity and area consumption increase significantly
Solution Approach 1:
The patent segments the threshold detection function into two separate latches with different threshold levels (first threshold level and second threshold level) instead of using a single latch. This segmentation allows the system to detect transitions more reliably by comparing the input signal against multiple thresholds, thereby improving MTBF while avoiding the need for multiple cascaded flip-flops
Solution Approach 2:
The patent changes the parameter of threshold levels by using two distinct threshold levels (first threshold level and second threshold level) instead of a single threshold level. This parameter change enables more robust transition detection across different clock domains, improving reliability without increasing device complexity
2Reliability
If the number of cascaded flip flops is increased to reduce MTBF in high clock frequency applications, then the reliability improves, but the area consumption and device complexity increase
Solution Approach 1:
The patent divides the reliability enhancement function into two parallel latches with different threshold levels rather than using multiple cascaded flip-flops. This segmentation achieves improved MTBF through threshold diversity while maintaining a compact area footprint
Solution Approach 2:
The patent merges the functions of multiple flip-flops into a single data storage element that uses two latches with different threshold levels. This merging achieves the same reliability improvement as multiple flip-flops but with significantly reduced area consumption
3Reliability
If multiple cascaded flip flops are used for clock-domain crossing, then the mean time between failures (MTBF) is reduced, but the manufacturing cost increases
Solution Approach 1:
The patent segments the reliability function into two threshold-level latches within a single data storage element, reducing the total component count compared to multiple cascaded flip-flops. This segmentation lowers manufacturing complexity and cost while maintaining improved MTBF
Solution Approach 2:
The patent combines multiple reliability-enhancing flip-flops into a single integrated data storage element with two latches operating at different threshold levels. This merging reduces manufacturing cost by decreasing the number of discrete components and interconnections required
4Area of stationary object
If conventional single threshold level data storage elements are used, then the circuit area is minimized, but the failure rate increases due to metastability
Solution Approach 1:
The patent changes the threshold level parameter by introducing two distinct threshold levels (first threshold level and second threshold level) into the data storage element. This parameter change reduces failure rate by providing more robust transition detection while maintaining minimal area consumption through a single integrated element
5Reliability
If the number of flip flops is increased to handle high clock frequencies above 800 MHz, then the reliability improves, but the device complexity and manufacturing complexity increase
Solution Approach 1:
The patent uses two distinct threshold levels to improve reliability for high clock frequency applications above 800 MHz, avoiding the need for five or more cascaded flip-flops. This parameter change maintains low device complexity while achieving the required reliability
Data Source
AI summary
A data storage element comprises a master stage (MS) with a first and a second latch (LI, L2), an error stage (ES) and a slave stage (SLS). The first latch (LI) generates in a clocked fashion based on a clock signal (CLK, CLKT, CLKB) a first logical signal (DOUT1) based on an input signal (DATA) in relation to a first threshold level (TP1). The second latch generates (L2) in a clocked fashion based on the clock signal (CLK, CLKT, CLKB) a second logical signal (DOUT2) based on the input signal (DATA) in relation to a second threshold level (TP2). The second threshold level (TP2) is distinct from the first threshold level (TP1). The error stage provides an error signal (ER) with a first logical state if the first and the second logical signal (DOUT1 , DOUT2) have the same logical state, and with a second logical state they have different logical states. The slave stage (SLS) sets an output value (Q) of the data storage element to a common logical state of the first and the second logical signal (DOUT1 , DOUT2) when the error signal (ER) has the first logical state, and keeps the output value (Q) unchanged otherwise.