Dual-Threshold Clock Control for Fast Voltage Droop Regulation
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Solution Overview
Problem
Conventional power management integrated circuits (PMICs) have a response time that is excessively long in high-frequency applications, making them unable to effectively suppress voltage droop, which is critical in high-frequency scenarios.
Innovation Solution
A dual threshold clock control (DTCC) system that combines discrete-time ripple correlation correction (DRCC) and supply voltage scanning to regulate input voltage droops, using DRCC for fast-acting high-frequency droop mitigation and supply voltage scanning for mid-to-low frequency droop management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If PMIC is used for power management, then power management function is provided, but response time is excessively long (0.5 μs or more) making it unable to suppress voltage droop in high-frequency applications
Solution Approach 1:
The patent segments the voltage droop suppression function into two distinct mechanisms: a first mechanism (fast response circuit) for high-frequency applications with response time less than 0.5 μs, and a second mechanism (PMIC) for general power management. This segmentation allows each mechanism to be optimized for its specific frequency range, resolving the contradiction between response time and droop suppression capability.
2Measurement precision
If conventional PMIC remote sensing is used, then voltage sensing is provided, but response time is 0.5 μs or more which is too slow for high-frequency applications
Solution Approach 1:
The patent creates a segmented sensing architecture where a first sensing mechanism (fast response circuit) provides rapid voltage detection for high-frequency applications, while the second sensing mechanism (PMIC remote sensing) handles general voltage monitoring. This allows the system to maintain measurement precision across both fast and slow response paths.
Solution Approach 2:
The patent introduces an intermediary fast response circuit that acts as a mediator between the voltage source and the slow PMIC. This intermediary circuit provides immediate voltage sensing and droop suppression for high-frequency transients, while the PMIC handles steady-state power management, thus resolving the speed-precision contradiction.
3Device complexity
If a single mechanism is used for voltage droop regulation, then device complexity is reduced, but it cannot effectively handle both high-frequency and mid-to-low frequency droops
Solution Approach 1:
The patent segments the droop regulation function into a first mechanism for high-frequency droops and a second mechanism for mid-to-low frequency droops. This segmentation enables the system to handle a broad frequency spectrum effectively, demonstrating that increased functional segmentation can enhance adaptability even if it slightly increases device complexity.
Solution Approach 2:
The patent implements a dynamic switching mechanism that automatically selects between the first and second droop regulation mechanisms based on the detected droop frequency characteristics. This dynamic adaptation allows the system to optimize performance for different frequency ranges without requiring manual configuration, effectively resolving the contradiction between complexity and versatility.
Data Source
AI summary
Various examples with respect to dual threshold clock control are described. A method involves sensing an input voltage of a processing circuit with a first mechanism and a second mechanism different from the first mechanism. The method also involves regulating a first droop of the input voltage using the first mechanism. The method further involves regulating a subsequent droop of the input voltage after the first droop using the second mechanism.