Dual-Threshold Delay Circuit for MOS Aging Compensation
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Solution Overview
Problem
MOS transistor aging, particularly NBTI, causes performance degradation and reliability issues in EEPROMs and timer circuits, leading to inaccurate timing and potential device failure.
Innovation Solution
A detector circuit with a first and second detector, where the second detector is enabled only when the first detector reaches its activation threshold, and a logic circuit performs a logical operation on their outputs to ensure the output is asserted only when both detectors agree, mitigating the effects of transistor aging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single detector is used to detect the end of capacitor charging, then the device complexity is low, but the measurement precision degrades due to MOS transistor aging causing threshold voltage shifts
Solution Approach 1:
The detector circuit is segmented into two separate detectors: a first detector that detects when the capacitor voltage reaches a first threshold voltage, and a second detector that detects when the capacitor voltage reaches a second threshold voltage. This segmentation allows each detector to be optimized for specific threshold detection, compensating for aging effects through the combined output logic while maintaining manageable individual circuit complexity.
Solution Approach 2:
A logic circuit acts as an intermediary between the two detectors and the final output. The logic circuit receives outputs from both detectors and combines them to produce the final timing signal, mediating the information from both threshold detections to achieve accurate timing measurement that compensates for individual detector aging.
2Productivity
If the gate oxide thickness is reduced to scale down transistor size, then the productivity increases, but the reliability decreases due to accelerated TDDB and increased leakage currents
Solution Approach 1:
The patent changes the operating parameters of the MOS transistors by applying elevated temperatures and high voltages to intentionally accelerate aging mechanisms. This parameter change allows the system to predict and compensate for future degradation, enabling continued use of scaled transistors while maintaining reliability through proactive correction.
Solution Approach 2:
The system performs preliminary aging stress tests on the transistors before actual operation to establish baseline degradation characteristics. This preliminary action allows the system to predict future threshold voltage shifts and adjust operating parameters in advance, enabling continued use of scaled transistors without reliability loss.
3Measurement precision
If elevated temperatures and high voltages are applied to accelerate aging for characterization, then the measurement of aging effects improves, but the transistor degradation accelerates
Solution Approach 1:
The patent converts the harmful effect of accelerated degradation into a beneficial measurement tool. By intentionally subjecting transistors to elevated temperatures and high voltages, the system accelerates aging to measurable levels, allowing characterization of degradation mechanisms that would otherwise take years to manifest, thereby enabling compensation strategies.
Data Source
AI summary
Disclosed herein is a detector circuit including a first detector configured to receive an input signal and generate a first detector output signal indicative of the input signal having reached a first activation threshold and a second detector configured to receive the input signal and, when enabled by the first detector output signal, generate a second detector output signal indicative of the input signal having reached a second activation threshold. A logic circuit is configured to perform a logical operation on the first and second detector output signals to generate an output indicative of the input signal having reached a voltage equal to the second activation threshold.