Dual-Threshold FinFET Gate Structures for RF Linearity
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Solution Overview
Problem
Conventional integrated circuits, particularly finFETs, exhibit poor linearity due to nonlinear transconductance, which affects their performance as amplifiers and introduces issues like gain compression and intermodulation, especially in radio frequency devices.
Innovation Solution
The fabrication of integrated circuits with multiple gate devices featuring dual threshold voltages by forming distinct doped regions and gate structures on opposite sidewalls of semiconductor fin structures, allowing for different threshold voltages and improved linearity through selective doping and varying work functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar transistors are used to achieve simple manufacturing, then manufacturing ease is improved, but linearity performance deteriorates due to nonlinear transconductance
Solution Approach 1:
The transistor gate is segmented into two separate gates (first gate and second gate) positioned on opposite sidewalls of the fin structure. This segmentation allows independent control of threshold voltages and transconductance characteristics, enabling linear operation while maintaining compatibility with standard fabrication processes
Solution Approach 2:
Different doped regions are created on opposite sidewalls of the fin structure, with each sidewall having distinct doping concentrations and types. This local differentiation enables each gate to have tailored threshold voltage and transconductance characteristics, achieving overall linear operation through coordinated local properties
2Speed
If transistor size is reduced to increase switching speed, then speed performance is improved, but linearity deteriorates due to enhanced nonlinear effects at smaller dimensions
Solution Approach 1:
The dual-gate structure enables dynamic control of the channel through independent gating, allowing the transistor to operate in different regimes (linear or nonlinear transconductance) depending on the applied voltages. This dynamic control maintains linearity even at reduced device dimensions
Solution Approach 2:
By independently adjusting the threshold voltages of the first and second gates through selective doping, the transconductance characteristics can be optimized for linear operation. The parameter changes in doping concentration and gate voltage enable linearity maintenance at smaller transistor sizes
3Reliability
If multiple gates are formed on opposite sidewalls with different doping, then linearity is improved through dual threshold voltages, but device complexity increases
Solution Approach 1:
The first and second gates are merged into a single integrated structure that wraps around opposite sidewalls of the fin. This merging reduces the number of discrete components and simplifies the overall device architecture while maintaining the dual-gate functionality and linear operation characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces second-order transconductance nonlinearity by over 90% compared to conventional transistors, enhancing the linearity of amplifier devices and enabling higher device densities with reduced power consumption.
Implementation Method 1
forming a first doped region along the first sidewall and forms a second doped region along the second sidewall
Data Source
AI summary
Integrated circuits including multiple gate devices with dual threshold voltages and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes providing a semiconductor fin structure overlying a semiconductor substrate. The semiconductor fin structure has a first sidewall, a second sidewall opposite the first sidewall, and an upper surface. The method includes forming a first gate along the first sidewall of the semiconductor fin structure with a first threshold voltage. Further, the method includes forming a second gate along the second sidewall of the semiconductor fin structure with a second threshold voltage different from the first threshold voltage.