Dual Time Domain Control for Dynamic Staggering in Flash Memory
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Solution Overview
Problem
Flash storage devices face challenges in managing peak current draws during program operations, which can exceed the maximum current supply capacity, potentially affecting device functionality and leading to storage errors.
Innovation Solution
A memory controller dynamically staggers the operation of memory dies by monitoring alarm signals and transmitting postpone signals to prevent synchronous peak current draws, using a dual time domain control mechanism to manage current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory dies operate synchronously during program operations, then productivity is improved, but peak current draw exceeds maximum current supply capacity
Solution Approach 1:
The controller implements periodic staggering of program operations across multiple memory dies by using alarm signals to detect when dies are entering high-current states and postponing subsequent dies until the current draw decreases. This creates a periodic pattern where dies operate in staggered phases rather than simultaneously, reducing peak current while maintaining overall productivity.
Solution Approach 2:
The system dynamically adjusts the operation timing of memory dies based on real-time current draw conditions. The controller monitors alarm signals from each die and dynamically postpones the start of program operations for subsequent dies when peak current thresholds are approached, creating adaptive, dynamic scheduling rather than fixed synchronous operation.
2Productivity
If memory dies operate synchronously during program operations, then productivity is improved, but reliability deteriorates due to voltage drops affecting device functionality
Solution Approach 1:
The controller uses alarm signals from memory dies as feedback indicators that a die is entering a high-current operational state. When the controller receives alarm signals within a threshold time window, it postpones subsequent program operations to prevent excessive current draw and voltage drops, thereby maintaining reliable device operation while preserving productivity through coordinated scheduling.
3Power
If the controller monitors and manages each memory die operation individually, then current draw is controlled, but device complexity increases
Solution Approach 1:
The controller uses a universal alarm signal mechanism that can be applied to any number of memory dies through common signal lines. The same alarm signal and postpone signal protocols are used regardless of the number of dies, allowing the controller to manage current draw across multiple dies without proportionally increasing complexity. The system handles N dies using the same basic monitoring and control logic.
Data Source
AI summary
Aspects of a storage device including a memory and a controller are provided. The memory can include memory dies that draw a current from a current source during a program operation. The controller may monitor for an alarm signal from the memory dies on a first common channel between the controller and the memory dies. The alarm signal indicates that a corresponding memory die is entering an operational state that draws a peak current from the current source for the program operation. The controller can receive, from the memory dies, one or more alarm signals on the first common channel within a predetermined threshold time. The controller can transmit a postpone signal on a second common channel to the memory dies based on the one or more alarm signals received within the predetermined threshold time.