Dual Time-Domain Timestamp Correction for TSN Backplane I/O
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Solution Overview
Problem
Industrial control systems face disruptions and critical issues due to desynchronization in the Precision Time Protocol (PTP) master time domain, leading to communication disruptions and loss of sub-microsecond time precision in end devices.
Innovation Solution
An industrial system that includes a microcontroller and two time modules from different domains, generating timestamps and calculating an offset and clock ratio to transmit corrections to I/O modules, allowing for timestamping correction and maintaining sub-microsecond precision without time resynchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If PTP time synchronization is used to maintain sub-microsecond precision, then time precision is improved, but communication disruptions occur when desynchronization happens in the master time domain
Solution Approach 1:
The system divides time domain management into two independent segments: the PTP master time domain for synchronization and a local timestamp domain for precise event marking. By segmenting the time reference sources, the patent isolates the impact of desynchronization to prevent system-wide communication disruptions while maintaining sub-microsecond precision for critical measurements.
Solution Approach 2:
The patent introduces an intermediary mechanism that captures and stores absolute timestamps from the PTP master clock before desynchronization occurs. This intermediary timestamp storage acts as a buffer that continues to provide accurate time references even when the PTP synchronization fails, preventing communication disruptions.
2Measurement precision
If time resynchronization is performed to maintain precision, then time precision is improved, but communication interruptions occur during the resynchronization process
Solution Approach 1:
The system performs preliminary timestamp capture by continuously recording absolute time values from the PTP master clock before any desynchronization or resynchronization events occur. These pre-captured timestamps are stored and made available immediately, eliminating the need to wait for resynchronization and thus preventing communication interruptions.
Solution Approach 2:
The patent implements a cushioning mechanism by maintaining a buffer of pre-captured timestamps that can be used during resynchronization events. This buffer acts as a protective cushion that ensures continuous time reference availability without interruption, preventing communication losses during the resynchronization process.
3Device complexity
If a common time reference is used for all devices, then synchronization is simplified, but a single point of failure is created in the master time domain
Solution Approach 1:
The patent segments the time reference architecture into a master PTP time domain for synchronization coordination and multiple independent local timestamp domains for actual time-stamping operations. This segmentation eliminates the single point of failure in the master domain while maintaining synchronization simplicity through the use of standardized PTP protocols.
Solution Approach 2:
The system introduces an intermediary timestamp storage layer that decouples the master PTP time domain from the local time-stamping functions. This intermediary layer captures and preserves absolute timestamps independently, so when the master domain fails, the local intermediaries continue to provide accurate time references without affecting overall system reliability.
Data Source
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AI summary
The invention relates to an industrial system for controlling backplane communication, comprising: a microcontroller (MC), a first time module (TM1) belonging to a first time domain and generating a first timestamp (tsli) at an event, a second time module (TM2) belonging to a second time domain and able to communicate with at least one Input/Output, I/O, module (IOM), generating a second timestamp (ts2i) at the event, wherein the microcontroller (MC), the first time module (TM1) and the second time module (TM2) are included in a control manager (CM) able to communicate with at least one Input/Output, I/O, module (IOM), wherein the microcontroller (MC) is configured to: calculate an offset (OSi) between the second timestamp and the first timestamp, compute a clock ratio (cri) between the second time domain and the first time domain, transmit a message to said at least one I/O module (IOM), the message comprising the second timestamp (ts2i), the offset (OSi) and the clock ratio (cri).