Dual Timestamp Clock Synchronization With Lower Link Bandwidth
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Solution Overview
Problem
Existing IP clock synchronization technologies, such as IEEE 1588 PTP, occupy excessive link bandwidth resources and interfere between frequency and time synchronization, especially when network conditions deteriorate and only one timestamp engine is present at the slave clock side.
Innovation Solution
Implementing a method and system that uses two distinct timestamp engines - a relative timestamp engine and an absolute timestamp engine - to independently perform frequency and time synchronization, allowing for asynchronous clock frequency adjustment and time offset calculation without interfering with each other, thereby reducing bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional IP clock synchronization technology (IEEE 1588 PTP) is used to perform frequency and time synchronization, then clock synchronization accuracy is improved, but link bandwidth resources are excessively occupied
Solution Approach 1:
The patent segments the single timestamp engine into two independent timestamp engines: a first timestamp engine dedicated to frequency synchronization and a second timestamp engine dedicated to time synchronization. This segmentation allows each engine to operate independently with optimized packet transmission, reducing overall bandwidth consumption while maintaining synchronization accuracy.
Solution Approach 2:
The patent creates a universal timestamp acquisition system where multiple timestamp engines can handle different synchronization functions (frequency and time) simultaneously. Each engine serves its specific function while contributing to the overall synchronization system, enabling multi-functionality without resource conflicts.
2Reliability
If packet transmission frequency is increased to maintain synchronization under deteriorated network conditions, then synchronization reliability is improved, but link bandwidth resources are excessively occupied
Solution Approach 1:
The patent divides the synchronization task into two independent streams with different packet frequencies: frequency synchronization uses a first packet transmission frequency while time synchronization uses a second packet transmission frequency. This segmentation allows optimization of packet rates for each function, maintaining reliability without excessive bandwidth consumption.
3Device complexity
If only one timestamp engine exists at the slave clock side, then device complexity is reduced, but frequency synchronization and time synchronization interfere with each other
Solution Approach 1:
The patent segments the single timestamp engine into two independent engines that operate separately for frequency and time synchronization. This segmentation eliminates interference between the two synchronization processes, as each engine independently timestamps packets for its specific function without affecting the other.
Solution Approach 2:
The patent introduces an intermediary mechanism where the first and second timestamp engines operate independently but both contribute to the overall synchronization system. This intermediary structure allows frequency and time synchronization to proceed without mutual interference while maintaining system coherence.
Data Source
AI summary
A precise-clock synchronization method and system and a precise-clock frequency/time synchronization device are provided. In the embodiments of the present invention, two time stamp engines are provided at a slave clock side. A relative time stamp engine provides a relative arrival time stamp. An absolute time stamp engine provides an absolute arrival time stamp. The frequency/time synchronization is calculated by using different time stamps obtained from different time stamp engines, so the frequency synchronization and time synchronization of the master clock and the slave clock may be separately accomplished, and one synchronization function may be enabled or disabled. Therefore, the frequency synchronization and time synchronization of the master clock and the slave clock do not interfere with each other, thus greatly reducing the occupied link bandwidth resources.