Dual TLB Arrays for Variable Page Size Translation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional address translation schemes in computer systems face performance issues due to the need to check multiple page sizes in translation lookaside buffers (TLBs), leading to reduced lookup speed, peak TLB bandwidth, and increased latency, especially when supporting multiple page sizes like 4 KB, 64 KB, and 1 GB.
Innovation Solution
Implementing a dual TLB array system where one TLB array is configured for smaller page sizes and another for larger page sizes, using the least significant bit (LSB) of the effective address to determine which array to use for lookup, allowing concurrent searches across both arrays to minimize delays and maintain efficient caching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple page sizes are supported in a single TLB array, then address translation versatility is improved, but lookup speed and TLB bandwidth deteriorate due to the need to check all possible page sizes
Solution Approach 1:
The patent divides the single TLB array into multiple separate TLB arrays, with each array dedicated to a specific page size. This segmentation allows the system to support multiple page sizes (improving versatility) while enabling direct lookup in the appropriate array based on the page size indicator in the virtual address (maintaining lookup speed). The segmentation eliminates the need to check all possible page sizes by organizing TLB entries into size-specific groups.
2Speed
If dedicated TLB arrays are created for each page size, then lookup speed is improved, but device complexity and memory usage increase
Solution Approach 1:
The patent designs each TLB array to have a uniform structure that can handle any page size, making them universally applicable. The arrays are identical in organization and access mechanism, differing only in the page size they are optimized for. This universal design reduces overall complexity by avoiding the need for different array structures for different page sizes, while still providing dedicated arrays for each page size to maintain lookup speed.
3Device complexity
If a single TLB array is used for all page sizes, then device complexity is reduced, but TLB bandwidth and hit latency worsen due to sequential checking
Solution Approach 1:
The patent segments the TLB into multiple parallel arrays, each dedicated to a specific page size. This segmentation enables simultaneous lookup operations across different page size arrays, effectively doubling or tripling the TLB bandwidth depending on the number of arrays. The segmented structure allows the system to process multiple translation requests in parallel, significantly improving productivity while maintaining manageable complexity through standardized array designs.
4Ease of manufacture
If multiple page sizes are checked sequentially in a single TLB, then implementation simplicity is maintained, but table walk initiation latency increases
Solution Approach 1:
The patent uses the page size indicator bit in the virtual address to pre-select the appropriate TLB array before the lookup operation begins. This preliminary selection action eliminates the need for sequential checking of multiple page sizes, reducing table walk initiation latency. The system prepares the correct array for access in advance based on the page size information already present in the address, making the translation process faster while maintaining implementation simplicity through straightforward address-based selection logic.
Data Source
AI summary
A computer system includes a translation lookaside buffer (TLB) and a processor. The TLB comprises a first TLB array and a second TLB array, and stores entries comprising virtual address information and corresponding real address information. The processor is configured to receive a first virtual address for translation, and to concurrently determine if the TLB stores a physical address associated with the first virtual address based on a first portion and a second portion of the first virtual address. The first portion is associated with a first page size and the second portion is associated with a second page size (different from the first page size). The first portion is used to perform lookup in either one of the first TLB array and the second TLB array and the second portion is used for performing lookup in other one of the first TLB array and the second TLB array.