Dual-Tone Signal Decoder Using Cycle Counting
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Solution Overview
Problem
Existing methods for decoding dual-tone signals struggle with asynchronous clocks, requiring complex division operations and being unsuitable for devices without processors, especially when dealing with tolerance and noise in communication systems.
Innovation Solution
A dual-tone signal decoding method and apparatus that uses counters and state control logic to detect and decode tones without performing division, allowing for decoding with a large tolerance and without the need for division operations, utilizing counters to measure cycles of tones and comparing them to thresholds to identify events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If division operations are performed to decode dual-tone signals, then frequency ratio calculation is achieved, but device complexity increases and processing becomes unsuitable for devices without processors
Solution Approach 1:
The patent replaces the computational division operation with a mechanical counter-based system. Counters count cycles of the first and second tones independently, and the decoder compares these counts directly without performing division. This substitution of computational mechanics with counting mechanics resolves the contradiction by maintaining measurement precision while eliminating complex division operations.
Solution Approach 2:
The patent changes the parameter representation from continuous frequency values requiring division to discrete cycle counts that can be directly compared. By measuring and comparing the number of cycles of each tone rather than dividing their frequencies, the system achieves the same decoding function without computational complexity.
2Adaptability or versatility
If asynchronous clocks with large tolerance are used, then clock synchronization flexibility is improved, but frequency estimation accuracy deteriorates
Solution Approach 1:
The patent implements a self-service mechanism where the system automatically adapts to clock tolerance by counting cycles relative to each other. The counters naturally accommodate asynchronous clocks with large tolerance because they measure the actual number of cycles occurring, regardless of timing variations. This eliminates the need for precise frequency estimation while maintaining adaptability to clock variations.
Solution Approach 2:
The patent uses excessive counting action by counting all cycles of each tone over their respective durations, rather than attempting to estimate frequencies. This partial measurement approach (counting discrete cycles) is more robust to timing variations than continuous frequency estimation, resolving the contradiction between adaptability and precision.
3Device complexity
If cycle counting with thresholds is used instead of division, then device simplicity is improved, but decoding accuracy may deteriorate
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing threshold values that correspond to different events. During decoding, the system simply compares the counted cycles against these pre-established thresholds without requiring complex real-time calculations. This maintains decoding accuracy while preserving operational simplicity.
Solution Approach 2:
The patent uses simple, disposable-like comparison operations instead of expensive, complex division operations. The threshold comparison is a simple, fast operation that can be performed without sophisticated processors, maintaining accuracy while dramatically reducing device complexity and operational requirements.
Data Source
AI summary
Methods and apparatus to decode dual-tone signals are disclosed. An example receiver to decode a dual-tone signal includes a tone detector to detect a start of a first tone, a first counter to count first cycles of the first tone, a second counter to count second cycles of a system clock while the first counter is counting and the first count is less than a first threshold, state control logic to start the second counter counting third cycles of the clock when a time period elapses, the third count being substantially equal to the second count, the first counter to count fourth cycles of a second tone while the third cycles are counted, and a decoder to compare the fourth count to a second threshold to identify an event represented by the signal.