Dual-Transistor MRAM Cell for Area Reduction
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Solution Overview
Problem
Existing memory technologies face challenges in reducing memory size while maintaining high bandwidth and supporting dual-port features, often leading to increased read latency or larger memory areas.
Innovation Solution
The use of two transistors and two bit lines, where both transistors are turned on during writing and one during reading, to provide a write current that is less than the storage element's write current but sufficient when used in parallel, allowing for a smaller transistor size and reduced memory area, while still supporting dual-port reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bandwidth is increased by increasing an input/output quantity of the storage array, then the bandwidth is improved, but the memory layout becomes flat and the read latency is increased
Solution Approach 1:
The storage array is divided into multiple banks (first bank and second bank), each capable of independent operation. This segmentation allows simultaneous read operations from different banks, increasing bandwidth without requiring a completely flat memory layout that would increase read latency within each bank.
2Productivity
If the bandwidth is increased by reducing an array size to increase a total quantity of arrays, then the bandwidth is improved, but the proportion of peripheral circuits increases and the area of the entire memory increases
Solution Approach 1:
Two transistors are merged to control a single storage element, with both transistors sharing control of the same storage element. This merging allows the memory to support dual-port operations and increase bandwidth while using fewer total transistors than would be required if separate transistors were used for each port, thereby reducing the overall memory area.
Solution Approach 2:
The two transistors controlling a single storage element serve multiple functions: they enable both single-port and dual-port operations, support both read and write operations, and provide flexibility in memory access modes. This multi-functionality increases bandwidth utilization without requiring additional dedicated circuits for each function.
3Area of stationary object
If two transistors are used to provide write current in parallel, then the transistor size is reduced and memory area is reduced, but the configuration must support both writing and reading operations
Solution Approach 1:
The system dynamically configures the operation mode by controlling the state of the two transistors. During write operations, both transistors are activated to provide sufficient write current. During read operations, only one transistor is activated to enable read access. This dynamic switching allows the same hardware configuration to support multiple operation modes without requiring separate dedicated circuits for each mode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a smaller memory area similar to conventional single-port memories while maintaining dual-port functionality, improving read operations and reducing overall memory size without compromising performance.
Implementation Method 1
when a magnetization orientation of the free layer 11 is the same as a magnetization orientation of the fixed layer 13, as shown in FIG. 1a, resistance of the MTJ has a relatively low resistance value. When the magnetization orientation of the free layer 11 is opposite to the magnetization orientation of the fixed layer 13, as shown in FIG. 1b, the resistance of the MTJ has a relatively high resistance value.
Implementation Method 2
Spin-transfer torque magnetic random access memory (STT-MRAM) is a novel memory with great potential
Data Source
AI summary
A memory and an electronic device are provided. The memory includes a storage element (10), a first transistor (21), a second transistor (22), a first bit line (BLA), and a second bit line (BLB). The storage element (10) is coupled to the first bit line (BLA) and the second bit line (BLB) by separately using the first transistor (21) and the second transistor (22), and the first transistor (21) and the second transistor (22) are turned on during a write operation. When the foregoing solution is used, compared with providing a required write current by using one transistor, providing the write current by using the two transistors may enable a smaller transistor to meet a requirement, thereby reducing an area required by the entire memory. In addition, the memory in this application can still support a dual-port feature in a read operation.