Dual Translation Map Architecture for Flash Memory Efficiency

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Solution Overview

Problem

Current data storage systems face inefficiencies in managing logical and physical resource mappings, particularly in garbage collection and data reconstruction processes, due to limitations in memory and computing power distribution between host devices and data storage devices.

Innovation Solution

Implementing two translation maps: a logical-to-logical translation map on the host device and a logical-to-physical translation map on the data storage device, allowing for efficient memory operations, garbage collection, and data reconstruction by distributing complex calculations and erase unit information accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single translation map is stored on the data storage device, then the device can manage physical resources, but the host device cannot efficiently perform complex logical mappings due to limited memory and computing power on the storage device

Engineering Contradiction:
Improvememory operation efficiencyVSAvoidtranslation map management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The translation map is divided into two separate maps: a logical-to-logical translation map stored on the host device for complex logical sector to logical erase unit mappings, and a logical-to-physical translation map stored on the data storage device for logical erase unit to physical erase unit mappings. This segmentation allows each device to store only the translation map necessary for its function, improving efficiency while reducing individual device complexity.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If all translation information is stored on the host device, then complex logical mappings can be performed, but the data storage device cannot efficiently perform physical erase unit management and data reconstruction

Engineering Contradiction:
Improvelogical mapping managementVSAvoiddata reconstruction time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The logical-to-physical translation map acts as an intermediary between the host device's logical-to-logical translation map and the data storage device's physical memory structures. This intermediate translation map enables the storage device to independently perform physical erase unit management and rapid data reconstruction without requiring constant communication with the host device.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If the logical-to-logical translation map is stored on the data storage device, then physical resource management is simplified, but the host device loses the ability to efficiently perform garbage collection operations

Engineering Contradiction:
Improvephysical resource management complexityVSAvoidgarbage collection efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The translation functionality is segmented between two maps stored in different locations. The logical-to-logical translation map is stored on the host device where it can be efficiently accessed by the garbage collection control engine for identifying valid data, while the logical-to-physical translation map is stored on the data storage device for physical resource management. This segmentation optimizes both garbage collection efficiency and physical resource management.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10942849B2Use of a logical-to-logical translation map and a logical-to-physical translation map to access a data storage device
Publication Date: 2021.03.09 GOOGLE LLC
  • US10942849B2 patent drawing
  • US10942849B2 patent drawing
  • US10942849B2 patent drawing

AI summary

An apparatus includes a host device and a data storage device. The host device is configured to store a first translation map for converting a logical sector to a logical erase unit. The data storage device includes a plurality of flash memory devices and a memory controller operationally coupled with the flash memory devices, each of the flash memory devices being arranged into a plurality of erase units, each of the erase units having a plurality of pages for storing data. The memory controller is configured to receive a second translation map from the host device, the second translation map for converting a logical erase unit to a physical erase unit within the flash memory devices, and store the second translation map in a memory module on the data storage device.