Dual Trench Isolation for Backside Contact Alignment in CMOS
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Solution Overview
Problem
In semiconductor structures, overlap concerns exist between backside power rails and source/drain contact structures, particularly when the spacing between nFET and pFET logic devices is small, and unwanted undercuts can occur during backside processing in regions with passive devices.
Innovation Solution
The semiconductor structure employs two trench isolation structures with different widths and dielectric materials, allowing for self-aligned isolation between backside contacts of different polarities and merged contacts for same-polarity FETs, thereby addressing overlap and undercut issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single trench isolation structure is used between all FETs, then manufacturing process is simple, but electrical isolation between backside contacts of different polarities is insufficient
Solution Approach 1:
The patent implements different trench isolation structures in different locations: a first trench isolation structure with first dielectric material between same-polarity FETs, and a second trench isolation structure with second dielectric material between opposite-polarity FETs. This local differentiation provides appropriate electrical isolation for each case, resolving the contradiction between isolation reliability and structure complexity.
Solution Approach 2:
The trench isolation system is segmented into two distinct structures: one for same-polarity FET isolation and another for opposite-polarity FET isolation. Each segment is optimized for its specific function, with different dielectric materials and geometries, thereby achieving reliable electrical isolation while maintaining manageable device complexity through functional segmentation.
2Productivity
If spacing between nFET and pFET is reduced to increase density, then productivity improves, but overlap between backside power rails and source/drain contacts occurs
Solution Approach 1:
The trench isolation structures are positioned and dimensioned to automatically provide self-aligned isolation between backside contacts and power rails. The isolation structures serve themselves by defining the boundaries of contact regions, eliminating the need for additional alignment steps and enabling reduced spacing without overlap issues.
Solution Approach 2:
The trench isolation structures act as intermediary elements between the backside power rails and source/drain contact structures. These isolation trenches prevent direct overlap and electrical interference, enabling closer spacing between nFET and pFET while maintaining reliable contact formation.
3Ease of manufacture
If conventional single trench isolation is used in passive device regions, then manufacturing is simple, but unwanted undercuts occur during backside processing
Solution Approach 1:
The patent applies different trench isolation configurations in passive device regions compared to logic regions. The isolation structures in passive regions are specifically designed with appropriate dielectric materials and geometries to prevent undercut formation during backside processing, while maintaining ease of manufacture through integration with the overall trench isolation process.
Data Source
AI summary
A semiconductor structure having two different trench isolation structures is provided. The first trench isolation structure is located in a space between each neighboring pair of first conductivity type field effect transistors (FETs) and between each neighboring pair of second conductivity type FETs. The second trench isolation structure is located in a space between each neighboring pair of first conductivity type FETs and second conductivity type FETs. The first and second trench isolations structures are designed to have different widths and contain compositionally different trench dielectric materials.