Dual Trench Isolation Structures for Flash Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for manufacturing isolation structures in semiconductor devices face challenges in achieving smaller device sizes while maintaining switching speed and signal clarity, requiring complex processes and structures that are difficult to manufacture and integrate.
Innovation Solution
A method for fabricating integrated circuit devices, specifically Flash memory devices, involving the formation of dual trench structures with different depths in peripheral and cell regions, using a sequence of dielectric layer formation, patterning, and etching processes that maintain compatibility with conventional technology and equipment, allowing for shallower trench depth in cell arrays without additional masking steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional isolation structure manufacturing methods are used, then device switching speed and signal clarity are maintained, but device size cannot be reduced further and manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor substrate into distinct cell regions and peripheral regions, each with different trench depths. The cell region receives shallower trenches while the peripheral region receives deeper trenches, allowing differentiated isolation strategies for different functional areas without requiring additional masking steps.
Solution Approach 2:
The patent implements different trench depths in different regions of the substrate. The cell region has shallower trenches optimized for memory cell isolation, while the peripheral region has deeper trenches for circuit isolation, allowing each region to have optimized properties for its specific function.
2Productivity
If device size is reduced to increase circuit density, then more devices fit on each wafer, but process limitations prevent further scaling and manufacturing becomes more difficult
Solution Approach 1:
The patent uses a single patterning step that selectively exposes only the peripheral region for deeper trench formation, while the cell region receives shallower trenches. This partial action approach allows differentiated trench depths without requiring full exposure and re-patterning, reducing process complexity.
Solution Approach 2:
The patent changes the etching parameters and trench depth parameters differently for cell and peripheral regions. By controlling the etch process to stop at different depths in different regions, the patent achieves optimized isolation for each region while maintaining compatibility with standard fabrication processes.
3Reliability
If deeper trenches are formed in all regions, then isolation performance is improved, but source line resistance increases and manufacturing complexity increases
Solution Approach 1:
The patent applies different trench depths to different regions: shallower trenches in the cell region minimize disruption to source lines and reduce resistance, while deeper trenches in the peripheral region provide adequate isolation for circuit elements. This local differentiation optimizes both isolation performance and electrical characteristics.
Solution Approach 2:
The patent segments the isolation strategy by region, recognizing that cell regions and peripheral regions have different isolation requirements. The cell region uses shallower trenches to maintain source line integrity, while peripheral regions use deeper trenches for circuit isolation, eliminating the need for uniform deep trenches across the entire substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device yields and integrates design rules for 90 nanometers and less, providing improved source line resistance and reducing manufacturing complexity, while maintaining compatibility with existing processes and equipment.
Implementation Method 1
subjecting the first trench region, including the first trench structure, and the second trench region with an etching process to continue to form the first trench structure from the first depth to a second depth
Implementation Method 2
forming a first dielectric layer (e.g., silicon dioxide) having a first thickness overlying a cell region and a second dielectric layer (e.g., silicon dioxide) having a second thickness overlying the peripheral region
Data Source
AI summary
A method for fabricating integrated circuit devices, e.g., Flash memory devices, embedded Flash memory devices. The method includes providing a semiconductor substrate, e.g., silicon, silicon on insulator, epitaxial silicon. In a specific embodiment, the semiconductor substrate has a peripheral region and a cell region. The method includes forming a first dielectric layer (e.g., silicon dioxide) having a first thickness overlying a cell region and a second dielectric layer (e.g., silicon dixode) having a second thickness overlying the peripheral region. In a specific embodiment, the cell region is for Flash memory devices and/or other like structures. The method forms a pad oxide layer overlying the first dielectric layer and forms a nitride layer overlying the pad oxide layer. The method includes patterning at least the nitride layer to expose a first trench region in the peripheral region and to expose a second trench region in the cell region, while a portion of the first dielectric layer having the first thickness in the cell region is maintained. The method includes forming a first trench structure having a first depth in the first trench region, while the portion of the first dielectric layer having the first thickness in the cell region protects the second trench region. The method includes removing the portion of the first dielectric layer to expose the second trench region. In a specific embodiment, the method includes subjecting the first trench region, including the first trench structure, and the second trench region with an etching process to continue to form the first trench structure from the first depth to a second depth and to form a second trench structure having a third depth within the second trench region. In the third depth is less than the second depth.