Dual Trench Isolated Selective Epitaxial Diode Array Fabrication
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Solution Overview
Problem
Current phase change memory devices face limitations in size reduction due to the need for high driving current and complex manufacturing processes, particularly with diodes acting as selectors, which are not compatible with standard CMOS processes, leading to interference and reduced yield.
Innovation Solution
A method and device that increase driving current and switching speed of diodes while minimizing crosstalk noise by using a p-type semiconductor substrate with defined diode and peripheral regions, forming an N+ buried layer, epitaxial layer, deep trench isolation, and shallow trench isolation, allowing concurrent manufacturing with CMOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If diodes are manufactured in separate processes after CMOS device manufacture, then diode driving current can be increased, but manufacturing complexity increases and yield decreases
Solution Approach 1:
The patent merges the diode manufacturing process with the CMOS device manufacturing process by forming both structures simultaneously from a common epitaxial layer. The diode array region and peripheral CMOS region are processed together through shared steps including epitaxial growth, ion implantation, and trench isolation formation, eliminating the need for separate post-CMOS diode fabrication processes.
Solution Approach 2:
The patent creates a universal manufacturing process that serves multiple functions: the same epitaxial layer forms both the diode structures and the CMOS device structures, and the same ion implantation and isolation processes serve both diode and CMOS regions. This multi-functional approach reduces overall manufacturing complexity while maintaining the high driving current capability of the diodes.
2Quantity of substance
If ion implantation is performed after CMOS device manufacture, then diode doping can be achieved, but interference with CMOS devices occurs
Solution Approach 1:
The patent segments the substrate into distinct diode array regions and peripheral CMOS device regions before performing ion implantation. By defining these regions in advance and using selective masking techniques, the ion implantation process can be applied selectively to only the diode regions, preventing dopant contamination of the CMOS device regions and eliminating interference between the two device types.
Solution Approach 2:
The patent performs preliminary region definition and masking setup before the ion implantation process. The diode array regions are pre-defined and protected with masks that prevent implantation in CMOS areas, ensuring that when ion implantation occurs, only the intended diode regions receive dopants. This preliminary preparation eliminates the harmful interference effect.
3Power
If bipolar transistors are used as selectors, then driving current increases, but chip size and design complexity increase
Solution Approach 1:
The patent replaces complex bipolar transistor structures with simpler diode structures that, while having shorter operational lifetime in some contexts, provide sufficient driving current for the application. The diodes achieve the necessary power delivery capability without requiring the complex multi-layer bipolar transistor architecture, thereby reducing chip area and simplifying design while meeting the driving current requirement.
4Object-generated harmful factors
If deep trench isolation is formed, then crosstalk noise between diodes is reduced, but manufacturing steps increase
Solution Approach 1:
The patent combines the deep trench isolation formation with the existing manufacturing process flow by integrating it into the same epitaxial growth and processing sequence. The isolation trenches are formed concurrently with the diode structure fabrication, using the same masking and etching steps, rather than adding separate isolation processing stages. This merging approach reduces crosstalk noise while minimizing the increase in manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of diodes with high driving current and fast switching speed using conventional CMOS processes, simplifying manufacturing and reducing interference between diode and CMOS devices, thereby improving the performance and yield of phase change memory devices.
Implementation Method 1
forming an N+ buried layer in the diode array region by performing an ion implantation process and an annealing process
Implementation Method 2
forming an N+ buried layer in the diode array region by performing an ion implantation process and an annealing process
Implementation Method 3
forming a semiconductor epitaxial layer on the N+ buried layer
Data Source
AI summary
Methods and devices associated with phase change memory include diodes operating as selector switches having a large driving current and high switching speed. A method of forming a semiconductor device includes providing a semiconductor substrate, defining a diode array region and a peripheral region on the semiconductor substrate, forming an N+ buried layer in the diode array region by performing an ion implantation process and an annealing process. The method also includes forming a semiconductor epitaxial layer on the N+ buried layer, forming deep trench isolations through the epitaxial layer and the N+ buried layer into a portion of the substrate in the first direction, and forming shallow trench isolations in the diode array region and in the peripheral region in the second direction. The shallow trench isolation has a depth equal to or greater than a thickness of the epitaxial layer.