Dual Trench Isolation for Gate Oxide Stress Reduction

Solution Overview

Problem

High voltage semiconductor devices, such as LDDMOS and DeMOS, face challenges with high drain resistance and hot carrier degradation, which degrade mixed signal performance and increase electrical stress on the gate oxide, particularly at scaled technology nodes.

Innovation Solution

The implementation of a dual trench isolation structure, where a shallow trench isolation is used alongside an ultra-shallow trench isolation, reduces the electrical field on the gate oxide and improves hot carrier reliability without degrading mixed signal performance, by optimizing the depth and location of the trench isolations underneath the gate-drain overlap region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If LDD region is used to increase breakdown voltage, then breakdown voltage is improved, but drain resistance increases and mixed signal performance degrades

Engineering Contradiction:

Improvebreakdown voltageVSAvoidmixed signal performance

Core Design Contradiction:

StrengthVSReliability

Solution Approach 1:

The isolation structure is segmented into two distinct trenches: a first shallow trench isolation and a second ultra-shallow trench isolation. This segmentation allows each trench to serve different functions - the first trench provides primary isolation while the second trench specifically addresses the gate-drain overlap region, thereby reducing electrical field stress on the gate oxide without requiring additional LDD regions that would increase drain resistance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The second ultra-shallow trench isolation is specifically positioned underneath the gate-drain overlap region to provide localized protection. This local quality approach targets the specific area where electrical field stress is highest, reducing hot carrier degradation and gate oxide stress without affecting other regions of the device that would otherwise require LDD structures.

Inventive Principle:

Principle #3Local quality

2Strength

If DeMOS device is used to achieve higher breakdown voltage, then breakdown voltage is improved, but hot carrier degradation increases and electrical field on gate oxide increases

Engineering Contradiction:

Improvebreakdown voltageVSAvoidelectrical field on gate oxide

Core Design Contradiction:

StrengthVSObject-affected harmful factors

Solution Approach 1:

The isolation structure is segmented into two distinct trenches: a first shallow trench isolation and a second ultra-shallow trench isolation. This segmentation allows each trench to serve different functions - the first trench provides primary isolation while the second trench specifically addresses the gate-drain overlap region, thereby reducing electrical field stress on the gate oxide without requiring additional LDD regions that would increase drain resistance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent converts the potentially harmful high electrical field in the gate-drain overlap region into a benefit by using the second ultra-shallow trench isolation to redirect and reduce the field. The trench structure acts as a field plate, spreading out the electrical field lines and reducing peak field stress on the gate oxide, thereby reducing hot carrier degradation while maintaining the high breakdown voltage capability.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Ease of manufacture

If standard STI process is used with same depth STIs, then manufacturing is simplified, but mixed signal performance worsens

Engineering Contradiction:

ImproveSTI process simplicityVSAvoidmixed signal performance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The isolation structure is segmented into two distinct trenches: a first shallow trench isolation and a second ultra-shallow trench isolation. This segmentation allows each trench to serve different functions - the first trench provides primary isolation while the second trench specifically addresses the gate-drain overlap region, thereby reducing electrical field stress on the gate oxide without requiring additional LDD regions that would increase drain resistance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the depth parameter of the second trench isolation to be ultra-shallow (smaller depth than the first trench), creating a dual-depth isolation structure. This parameter change allows the second trench to provide localized field reduction underneath the gate-drain overlap region while maintaining compatibility with standard STI manufacturing processes, thus improving mixed signal performance without significantly complicating fabrication.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS8097930B2Semiconductor devices with trench isolations

Publication Date: 2012.01.17 INFINEON TECHNOLOGIES AG

AI summary

In an embodiment, a semiconductor device is provided. The semiconductor device may include a first diffusion region, a second diffusion region an active region disposed between the first diffusion region and the second diffusion region, a control region disposed above the active region, a first trench isolation disposed laterally adjacent to the first diffusion region opposite to the active region, and a second trench isolation disposed between the second diffusion region and the active region. The second trench isolation may have a smaller depth than the first trench isolation.